Empathy List Archives

AA

Alan Ambrose

Thu, Jun 11, 2015 2:22 PM

Hi,

So that turns into 2 games:
How fast can you count?
How many digits can you get in 1 second?
<<<

A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy

Alan

Hi, >>> So that turns into 2 games: How fast can you count? How many digits can you get in 1 second? <<< A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy Alan

BC

Bob Camp

Fri, Jun 12, 2015 12:43 PM

Hi

Well, take the CPLD up to 100 MHz, and feed 20 ns pulses to the TDC’s RC, drive that into a cheap 24 bit sigma delta A/D and you have an easy 1 Fs. Do a little processing on multiple samples and you have 15 displayed digits.

=====

Of course everything past about 50 ps is just noise ….

It all depends on what you are after:

Resolution
Accuracy
Repeatability

The first one is easy in any system. The last one can fool you. The one in the middle is what you actually were after in most cases.

Bob

On Jun 11, 2015, at 10:22 AM, Alan Ambrose alan.ambrose@anagram.net wrote:

Hi,

So that turns into 2 games:
How fast can you count?
How many digits can you get in 1 second?
<<<

A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy

Alan

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Hi Well, take the CPLD up to 100 MHz, and feed 20 ns pulses to the TDC’s RC, drive that into a cheap 24 bit sigma delta A/D and you have an easy 1 Fs. Do a little processing on multiple samples and you have 15 displayed digits. ===== Of course everything past about 50 ps is just noise …. It all depends on what you are after: Resolution Accuracy Repeatability The first one is easy in any system. The last one can fool you. The one in the middle is what you actually were after in most cases. Bob > On Jun 11, 2015, at 10:22 AM, Alan Ambrose <alan.ambrose@anagram.net> wrote: > > Hi, > >>>> > So that turns into 2 games: > How fast can you count? > How many digits can you get in 1 second? > <<< > > A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy > > Alan > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

AK

Attila Kinali

Mon, Jun 15, 2015 10:14 PM

On Thu, 11 Jun 2015 14:22:58 +0000
Alan Ambrose alan.ambrose@anagram.net wrote:

A clever interpolator for frequency or TIC would kill it -
for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with
a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC
and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16
bit ADC - and 1pS should be easy

Which architecture for the FPGA do you have in mind? The delay
line method (which is the most common one for FPGAs) has an intrinsic
limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude
conversion by charging a capacitor (both include a Nutt interpolator).

Using this technique, it might be possible to get into the 1ps ballpark,
if the design is done carefully (according to Richard McCorkle, the
limiting factor for the PICTIC II was the ADC of the PIC, followed by
the stability of the reference clock).

		Attila Kinali

--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will remain.

On Thu, 11 Jun 2015 14:22:58 +0000 Alan Ambrose <alan.ambrose@anagram.net> wrote: > A clever interpolator for frequency or TIC would kill it - > for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with > a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC > and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 > bit ADC - and 1pS should be easy Which architecture for the FPGA do you have in mind? The delay line method (which is the most common one for FPGAs) has an intrinsic limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude conversion by charging a capacitor (both include a Nutt interpolator). Using this technique, it might be possible to get into the 1ps ballpark, if the design is done carefully (according to Richard McCorkle, the limiting factor for the PICTIC II was the ADC of the PIC, followed by the stability of the reference clock). Attila Kinali -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain.

BC

Bob Camp

Mon, Jun 15, 2015 11:31 PM

Hi

Coming up with a reference clock can be harder than you might think.

Most of the jitter numbers you see published on frequency sources are based on a
“jitter mask” that runs from (maybe) 10 KHz up to 20 MHz. That’s fine for a specific
telecom need. It may not in any way apply to capturing a 1 pps pulse. IF you believe
the phase noise to jitter integration stuff (and there are reasons not to) the jitter goes way
up as you integrate closer to carrier. A 0.1 ps source can quickly turn into a 10 or 100 ps
source with a change of the lower bound on the jitter mask.

Now, once you have the jitter number, you are only part way to knowing it’s impact on
your measurement. There are always more things to consider.

Bob

On Jun 15, 2015, at 6:14 PM, Attila Kinali attila@kinali.ch wrote:

On Thu, 11 Jun 2015 14:22:58 +0000
Alan Ambrose alan.ambrose@anagram.net wrote:

A clever interpolator for frequency or TIC would kill it -
for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with
a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC
and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16
bit ADC - and 1pS should be easy

Which architecture for the FPGA do you have in mind? The delay
line method (which is the most common one for FPGAs) has an intrinsic
limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude
conversion by charging a capacitor (both include a Nutt interpolator).

Using this technique, it might be possible to get into the 1ps ballpark,
if the design is done carefully (according to Richard McCorkle, the
limiting factor for the PICTIC II was the ADC of the PIC, followed by
the stability of the reference clock).

		Attila Kinali

--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will remain.

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Hi Coming up with a reference clock can be harder than you might think. Most of the jitter numbers you see published on frequency sources are based on a “jitter mask” that runs from (maybe) 10 KHz up to 20 MHz. That’s fine for a specific telecom need. It may not in any way apply to capturing a 1 pps pulse. *IF* you believe the phase noise to jitter integration stuff (and there are reasons not to) the jitter goes way up as you integrate closer to carrier. A 0.1 ps source can quickly turn into a 10 or 100 ps source with a change of the lower bound on the jitter mask. Now, once you have the jitter number, you are only part way to knowing it’s impact on your measurement. There are *always* more things to consider. Bob > On Jun 15, 2015, at 6:14 PM, Attila Kinali <attila@kinali.ch> wrote: > > On Thu, 11 Jun 2015 14:22:58 +0000 > Alan Ambrose <alan.ambrose@anagram.net> wrote: > >> A clever interpolator for frequency or TIC would kill it - >> for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with >> a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC >> and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 >> bit ADC - and 1pS should be easy > > Which architecture for the FPGA do you have in mind? The delay > line method (which is the most common one for FPGAs) has an intrinsic > limit around 10-20ps. But the SR620 and the PICTIC use both a time to amplitude > conversion by charging a capacitor (both include a Nutt interpolator). > > Using this technique, it might be possible to get into the 1ps ballpark, > if the design is done carefully (according to Richard McCorkle, the > limiting factor for the PICTIC II was the ADC of the PIC, followed by > the stability of the reference clock). > > Attila Kinali > > -- > I must not become metastable. > Metastability is the mind-killer. > Metastability is the little-death that brings total obliteration. > I will face my metastability. > I will permit it to pass over me and through me. > And when it has gone past I will turn the inner eye to see its path. > Where the metastability has gone there will be nothing. Only I will remain. > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there.

BG

Bruce Griffiths

Tue, Jun 16, 2015 12:24 AM

Using an ADC to sample a triggered damped sinewave easily achieves 5ps
resolution (eg Keysight Acquiris). With a better optimised waveform model
and least squares fitting routine greater resolution is feasible.
The accuracy is dependent on the ADC sampling clock stability.
An optical frequency standard derived clock may be required to maintain
ps accuracy for long time intervals.

Bruce

On Tuesday, June 16, 2015 12:14:01 AM Attila Kinali wrote:

On Thu, 11 Jun 2015 14:22:58 +0000

Alan Ambrose alan.ambrose@anagram.net wrote:

A clever interpolator for frequency or TIC would kill it -
for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with
a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC
and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16
bit ADC - and 1pS should be easy

Which architecture for the FPGA do you have in mind? The delay
line method (which is the most common one for FPGAs) has an intrinsic
limit around 10-20ps. But the SR620 and the PICTIC use both a time to
amplitude conversion by charging a capacitor (both include a Nutt
interpolator).

Using this technique, it might be possible to get into the 1ps ballpark,
if the design is done carefully (according to Richard McCorkle, the
limiting factor for the PICTIC II was the ADC of the PIC, followed by
the stability of the reference clock).

		Attila Kinali

Using an ADC to sample a triggered damped sinewave easily achieves 5ps resolution (eg Keysight Acquiris). With a better optimised waveform model and least squares fitting routine greater resolution is feasible. The accuracy is dependent on the ADC sampling clock stability. An optical frequency standard derived clock may be required to maintain ps accuracy for long time intervals. Bruce On Tuesday, June 16, 2015 12:14:01 AM Attila Kinali wrote: > On Thu, 11 Jun 2015 14:22:58 +0000 > > Alan Ambrose <alan.ambrose@anagram.net> wrote: > > A clever interpolator for frequency or TIC would kill it - > > for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with > > a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC > > and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 > > bit ADC - and 1pS should be easy > > Which architecture for the FPGA do you have in mind? The delay > line method (which is the most common one for FPGAs) has an intrinsic > limit around 10-20ps. But the SR620 and the PICTIC use both a time to > amplitude conversion by charging a capacitor (both include a Nutt > interpolator). > > Using this technique, it might be possible to get into the 1ps ballpark, > if the design is done carefully (according to Richard McCorkle, the > limiting factor for the PICTIC II was the ADC of the PIC, followed by > the stability of the reference clock). > > Attila Kinali

AK

Attila Kinali

Tue, Jun 16, 2015 8:01 AM

Hoi Bruce,

On Tue, 16 Jun 2015 12:24:34 +1200
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Using an ADC to sample a triggered damped sinewave easily achieves 5ps
resolution (eg Keysight Acquiris). With a better optimised waveform model
and least squares fitting routine greater resolution is feasible.
The accuracy is dependent on the ADC sampling clock stability.
An optical frequency standard derived clock may be required to maintain
ps accuracy for long time intervals.

Do you mean the technique that Panek et al. [1] are using?
IIRC he got that down to 0.5ps RMS now. And yes, the major
source of error is the oscillator, according to [2].
Ripamonti et al. showed in [3] that using an LC tank instead of an SAW
filter will result in something in the order of 2-10ps RMS (after
temperature compensation). So this system is in the same region as an well
designed time-to-amplitude converter based system.

I really wonder which one would be easier to build.

		Attila Kinali

[1] "Time interval measurement device based on surface acoustic wave filter
excitation, providing 1ps precision and stability", by Panek andProchazka, 2007
http://dx.doi.org/10.1063/1.2779217

[2] "Random Errors in Time Interval Measurement Based on SAW Filter Excitation",
by Panek, 2008
http://dx.doi.org/10.1109/TIM.2007.915465

[3] "High frequency, high time resolution time-to-digital converter employing
passive resonating circuits", by Ripamonti, Abba, Geraci, 2010
http://dx.doi.org/10.1063/1.3432002

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Hoi Bruce, On Tue, 16 Jun 2015 12:24:34 +1200 Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote: > Using an ADC to sample a triggered damped sinewave easily achieves 5ps > resolution (eg Keysight Acquiris). With a better optimised waveform model > and least squares fitting routine greater resolution is feasible. > The accuracy is dependent on the ADC sampling clock stability. > An optical frequency standard derived clock may be required to maintain > ps accuracy for long time intervals. Do you mean the technique that Panek et al. [1] are using? IIRC he got that down to 0.5ps RMS now. And yes, the major source of error is the oscillator, according to [2]. Ripamonti et al. showed in [3] that using an LC tank instead of an SAW filter will result in something in the order of 2-10ps RMS (after temperature compensation). So this system is in the same region as an well designed time-to-amplitude converter based system. I really wonder which one would be easier to build. Attila Kinali [1] "Time interval measurement device based on surface acoustic wave filter excitation, providing 1ps precision and stability", by Panek andProchazka, 2007 http://dx.doi.org/10.1063/1.2779217 [2] "Random Errors in Time Interval Measurement Based on SAW Filter Excitation", by Panek, 2008 http://dx.doi.org/10.1109/TIM.2007.915465 [3] "High frequency, high time resolution time-to-digital converter employing passive resonating circuits", by Ripamonti, Abba, Geraci, 2010 http://dx.doi.org/10.1063/1.3432002 -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson

BG

Bruce Griffiths

Tue, Jun 16, 2015 9:32 PM

On Tuesday, June 16, 2015 10:01:09 AM Attila Kinali wrote:

Hoi Bruce,

On Tue, 16 Jun 2015 12:24:34 +1200

Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Using an ADC to sample a triggered damped sinewave easily achieves

5ps

resolution (eg Keysight Acquiris). With a better optimised waveform

model

and least squares fitting routine greater resolution is feasible.
The accuracy is dependent on the ADC sampling clock stability.
An optical frequency standard derived clock may be required to

maintain

ps accuracy for long time intervals.

Do you mean the technique that Panek et al. [1] are using?

Not quite he used an impulse to excite a saw filter rather than switching
off the dc current feed to an inductor or the equivalent.

IIRC he got that down to 0.5ps RMS now. And yes, the major
source of error is the oscillator, according to [2].
Ripamonti et al. showed in [3] that using an LC tank instead of an SAW
filter will result in something in the order of 2-10ps RMS (after
temperature compensation). So this system is in the same region as an

well

designed time-to-amplitude converter based system.

The curve fitting algorithm they used is somewhat deficient as is the
switching method employed one can do much better provided one has
sufficient time or computing resources available. My crude testing using a
somewhat simplified diode switched current source powered by the signal
itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better
driver and higher resolution ADC with a lower noise input amplifier than the
input amplifier of the oscilloscope I used should improve the results
somewhat as would a better model for the damped sine signal.

I really wonder which one would be easier to build.

Keysight as far as I can tell used a discrete LC circuit to produce a damped
sine wave rather than the conventional TAC approach used in the lower
resolution Acquiris models.
Bruce

		Attila Kinali

[1] "Time interval measurement device based on surface acoustic wave

filter

excitation, providing 1ps precision and stability", by Panek

andProchazka,

2007 http://dx.doi.org/10.1063/1.2779217

[2] "Random Errors in Time Interval Measurement Based on SAW Filter
Excitation", by Panek, 2008
http://dx.doi.org/10.1109/TIM.2007.915465

[3] "High frequency, high time resolution time-to-digital converter
employing passive resonating circuits", by Ripamonti, Abba, Geraci, 2010
http://dx.doi.org/10.1063/1.3432002

On Tuesday, June 16, 2015 10:01:09 AM Attila Kinali wrote: > Hoi Bruce, > > On Tue, 16 Jun 2015 12:24:34 +1200 > > Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote: > > Using an ADC to sample a triggered damped sinewave easily achieves 5ps > > resolution (eg Keysight Acquiris). With a better optimised waveform model > > and least squares fitting routine greater resolution is feasible. > > The accuracy is dependent on the ADC sampling clock stability. > > An optical frequency standard derived clock may be required to maintain > > ps accuracy for long time intervals. > > Do you mean the technique that Panek et al. [1] are using? Not quite he used an impulse to excite a saw filter rather than switching off the dc current feed to an inductor or the equivalent. > IIRC he got that down to 0.5ps RMS now. And yes, the major > source of error is the oscillator, according to [2]. > Ripamonti et al. showed in [3] that using an LC tank instead of an SAW > filter will result in something in the order of 2-10ps RMS (after > temperature compensation). So this system is in the same region as an well > designed time-to-amplitude converter based system. > The curve fitting algorithm they used is somewhat deficient as is the switching method employed one can do much better provided one has sufficient time or computing resources available. My crude testing using a somewhat simplified diode switched current source powered by the signal itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better driver and higher resolution ADC with a lower noise input amplifier than the input amplifier of the oscilloscope I used should improve the results somewhat as would a better model for the damped sine signal. > I really wonder which one would be easier to build. Keysight as far as I can tell used a discrete LC circuit to produce a damped sine wave rather than the conventional TAC approach used in the lower resolution Acquiris models. Bruce > > Attila Kinali > > > [1] "Time interval measurement device based on surface acoustic wave filter > excitation, providing 1ps precision and stability", by Panek andProchazka, > 2007 http://dx.doi.org/10.1063/1.2779217 > > [2] "Random Errors in Time Interval Measurement Based on SAW Filter > Excitation", by Panek, 2008 > http://dx.doi.org/10.1109/TIM.2007.915465 > > [3] "High frequency, high time resolution time-to-digital converter > employing passive resonating circuits", by Ripamonti, Abba, Geraci, 2010 > http://dx.doi.org/10.1063/1.3432002

AK

Attila Kinali

Wed, Jun 17, 2015 7:08 AM

On Wed, 17 Jun 2015 09:32:23 +1200
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Do you mean the technique that Panek et al. [1] are using?

Not quite he used an impulse to excite a saw filter rather than switching
off the dc current feed to an inductor or the equivalent.

Is there any fundamental difference there?

IIRC he got that down to 0.5ps RMS now. And yes, the major
source of error is the oscillator, according to [2].
Ripamonti et al. showed in [3] that using an LC tank instead of an SAW
filter will result in something in the order of 2-10ps RMS (after
temperature compensation). So this system is in the same region as an

well

designed time-to-amplitude converter based system.

The curve fitting algorithm they used is somewhat deficient as is the
switching method employed one can do much better provided one has
sufficient time or computing resources available.

Can you give a description what you would do differently?

And yes, the two authors look like fresh graduate students who were told by
their professor to see whether they can reproduce Paneks results without
using a SAW filter.

My crude testing using a
somewhat simplified diode switched current source powered by the signal
itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better
driver and higher resolution ADC with a lower noise input amplifier than the
input amplifier of the oscilloscope I used should improve the results
somewhat as would a better model for the damped sine signal.

Hmm.. but the diode switched current source would need a quite steep
input pulse, wouldn't it? So some kind of pulse shaping would be
needed for a general circuit.

I also played with the idea to use a overtone crystal oscillator instead
of an LC tank, as this would probably give a higher temperature stability.

			Attila Kinali

--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will remain.

On Wed, 17 Jun 2015 09:32:23 +1200 Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote: > > Do you mean the technique that Panek et al. [1] are using? > > Not quite he used an impulse to excite a saw filter rather than switching > off the dc current feed to an inductor or the equivalent. Is there any fundamental difference there? > > IIRC he got that down to 0.5ps RMS now. And yes, the major > > source of error is the oscillator, according to [2]. > > Ripamonti et al. showed in [3] that using an LC tank instead of an SAW > > filter will result in something in the order of 2-10ps RMS (after > > temperature compensation). So this system is in the same region as an > well > > designed time-to-amplitude converter based system. > > > The curve fitting algorithm they used is somewhat deficient as is the > switching method employed one can do much better provided one has > sufficient time or computing resources available. Can you give a description what you would do differently? And yes, the two authors look like fresh graduate students who were told by their professor to see whether they can reproduce Paneks results without using a SAW filter. > My crude testing using a > somewhat simplified diode switched current source powered by the signal > itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better > driver and higher resolution ADC with a lower noise input amplifier than the > input amplifier of the oscilloscope I used should improve the results > somewhat as would a better model for the damped sine signal. Hmm.. but the diode switched current source would need a quite steep input pulse, wouldn't it? So some kind of pulse shaping would be needed for a general circuit. I also played with the idea to use a overtone crystal oscillator instead of an LC tank, as this would probably give a higher temperature stability. Attila Kinali -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain.

BG

Bruce Griffiths

Wed, Jun 17, 2015 8:53 AM

I used the output of a CMOS frequency divider to drive a capacitor coupled passive dual diode and resistor plus a parallel tank circuit comprising a 1uH powdered iron core (amidon #6) inductor and a 100pF silvered mica capacitor. The ADC used a 100MHz clock which also drove the frequency divider chain. The idea being to evaluate the performance of the ringing LC circuit and minimise the influence of the 100MHz ocxo.
A BAW crystal could be used as a filter replacing the SAW filter used by Panek.
Bruce

 On Wednesday, 17 June 2015 8:20 PM, Attila Kinali <attila@kinali.ch> wrote:

On Wed, 17 Jun 2015 09:32:23 +1200
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Do you mean the technique that Panek et al. [1] are using?

Not quite he used an impulse to excite a saw filter rather than switching
off the dc current feed to an inductor or the equivalent.

Is there any fundamental difference there?

IIRC he got that down to 0.5ps RMS now. And yes, the major
source of error is the oscillator, according to [2].
Ripamonti et al. showed in [3] that using an LC tank instead of an SAW
filter will result in something in the order of 2-10ps RMS (after
temperature compensation). So this system is in the same region as an

well

designed time-to-amplitude converter based system.

The curve fitting algorithm they used is somewhat deficient as is the
switching method employed one can do much better provided one has
sufficient time or computing resources available.

Can you give a description what you would do differently?

And yes, the two authors look like fresh graduate students who were told by
their professor to see whether they can reproduce Paneks results without
using a SAW filter.

My crude testing using a
somewhat simplified diode switched current source powered by the signal
itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better
driver and higher resolution ADC with a lower noise input amplifier than the
input amplifier of the oscilloscope I used should improve the results
somewhat as would a better model for the damped sine signal.

Hmm.. but the diode switched current source would need a quite steep
input pulse, wouldn't it? So some kind of pulse shaping would be
needed for a general circuit.

I also played with the idea to use a overtone crystal oscillator instead
of an LC tank, as this would probably give a higher temperature stability.

Attila Kinali

--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will remain.

time-nuts mailing list -- time-nuts@febo.com
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I used the output of a CMOS frequency divider to drive a capacitor coupled passive dual diode and resistor plus a parallel tank circuit comprising a 1uH powdered iron core (amidon #6) inductor and a 100pF silvered mica capacitor. The ADC used a 100MHz clock which also drove the frequency divider chain. The idea being to evaluate the performance of the ringing LC circuit and minimise the influence of the 100MHz ocxo. A BAW crystal could be used as a filter replacing the SAW filter used by Panek. Bruce On Wednesday, 17 June 2015 8:20 PM, Attila Kinali <attila@kinali.ch> wrote: On Wed, 17 Jun 2015 09:32:23 +1200 Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote: > > Do you mean the technique that Panek et al. [1] are using? > > Not quite he used an impulse to excite a saw filter rather than switching > off the dc current feed to an inductor or the equivalent. Is there any fundamental difference there? > > IIRC he got that down to 0.5ps RMS now. And yes, the major > > source of error is the oscillator, according to [2]. > > Ripamonti et al. showed in [3] that using an LC tank instead of an SAW > > filter will result in something in the order of 2-10ps RMS (after > > temperature compensation). So this system is in the same region as an > well > > designed time-to-amplitude converter based system. > > > The curve fitting algorithm they used is somewhat deficient as is the > switching method employed one can do much better provided one has > sufficient time or computing resources available. Can you give a description what you would do differently? And yes, the two authors look like fresh graduate students who were told by their professor to see whether they can reproduce Paneks results without using a SAW filter. > My crude testing using a > somewhat simplified diode switched current source powered by the signal > itself achieved a fitting noise of around 5ps with a 14 bit ADC. A better > driver and higher resolution ADC with a lower noise input amplifier than the > input amplifier of the oscilloscope I used should improve the results > somewhat as would a better model for the damped sine signal. Hmm.. but the diode switched current source would need a quite steep input pulse, wouldn't it? So some kind of pulse shaping would be needed for a general circuit. I also played with the idea to use a overtone crystal oscillator instead of an LC tank, as this would probably give a higher temperature stability. Attila Kinali -- I must not become metastable. Metastability is the mind-killer. Metastability is the little-death that brings total obliteration. I will face my metastability. I will permit it to pass over me and through me. And when it has gone past I will turn the inner eye to see its path. Where the metastability has gone there will be nothing. Only I will remain. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.

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Using CPLD/FPGA or similar for frequency