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IP cores for x310 USRP

MS
Mukherjee, Satrajit
Wed, Aug 24, 2016 10:26 AM

Hello,

I have a x310 type USRP and am currently working on the rfnoc-devel branch. I have Xilinx Vivado 2015.2. After setting up the environment and

trying to make X310_RFNOC_HGS, I get the following error which is given subsequently:

After that, I have a set of questions regarding the licenses I need.

This is what I get when I try to make:



rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ source setupenv.sh
Setting up X3x0 FPGA build environment (64-bit)...
bash: /opt/Xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh: No such file or directory

  • Vivado: Found (/opt/Xilinx/Vivado/2015.2/bin)

Environment successfully initialized.
rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ make X310_RFNOC_HGS
make -f Makefile.x300.inc bin NAME=X310_RFNOC_HGS ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16  RFNOC=1 X310=1 EXTRA_DEFS="ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16  RFNOC=1 X310=1"
make[1]: Entering directory `/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300'
Vivado v2015.2 (64-bit)

---=======================
BUILDER: Building IP ten_gig_eth_pcs_pma

---=======================
BUILDER: Staging IP in build directory...
Reserving IP location: /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma
BUILDER: Retargeting IP to part xc7k410tffg900-2...
BUILDER: Building IP...
WARNING: Default location for XILINX_VIVADO_HLS not found:

****** Vivado v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/../tools/scripts/viv_generate_ip.tcl

set xci_file        $::env(XCI_FILE)              ;

set part_name        $::env(PART_NAME)              ;

set gen_example_proj $::env(GEN_EXAMPLE)            ;

set synth_ip        $::env(SYNTH_IP)              ;

set ip_name [file rootname [file tail $xci_file]]  ;

file delete -force "$xci_file.out"

create_project -part $part_name -in_memory -ip

ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Wed Aug 24 12:03:22 2016...
Releasing IP location: /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma
make[1]: *** [/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] Error 1
make[1]: Leaving directory `/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300'
make: *** [X310_RFNOC_HGS] Error 2



So I have a few questions:

  1. I have the ten_gig_eth_pcs_pma ip core. But while opening a new xilinx  project, I cannot find the part

xc7k410tffg900-2 which seems to be because I dont have IP cores for Kintex 7. So how can I get IP cores for Kintex 7

which uses xc7k410tffg900-2 fpga? I only need the required licenses and not hardware support for Kintex 7.

A link to just the licenses would be extremely helpful.

  1. What are the other licenses I might need for writing my own computation engine for rfnoc_devel apart from the above?

  2. I got a warning stating that I do not have the Vivado_HLS. I do not think that it is critical to the specific problem that

I am having. But if it is so, can you suggest me a way to just get that part without garbling the installation?

                                                             Thank You.

Regards,

Satrajit

Hello, I have a x310 type USRP and am currently working on the rfnoc-devel branch. I have Xilinx Vivado 2015.2. After setting up the environment and trying to make X310_RFNOC_HGS, I get the following error which is given subsequently: After that, I have a set of questions regarding the licenses I need. This is what I get when I try to make: ----------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------------------------- rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ source setupenv.sh Setting up X3x0 FPGA build environment (64-bit)... bash: /opt/Xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh: No such file or directory - Vivado: Found (/opt/Xilinx/Vivado/2015.2/bin) Environment successfully initialized. rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ make X310_RFNOC_HGS make -f Makefile.x300.inc bin NAME=X310_RFNOC_HGS ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 RFNOC=1 X310=1 EXTRA_DEFS="ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 RFNOC=1 X310=1" make[1]: Entering directory `/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300' Vivado v2015.2 (64-bit) ======================================================== BUILDER: Building IP ten_gig_eth_pcs_pma ======================================================== BUILDER: Staging IP in build directory... Reserving IP location: /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma BUILDER: Retargeting IP to part xc7k410tffg900-2... BUILDER: Building IP... WARNING: Default location for XILINX_VIVADO_HLS not found: ****** Vivado v2015.2 (64-bit) **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/../tools/scripts/viv_generate_ip.tcl # set xci_file $::env(XCI_FILE) ; # set part_name $::env(PART_NAME) ; # set gen_example_proj $::env(GEN_EXAMPLE) ; # set synth_ip $::env(SYNTH_IP) ; # set ip_name [file rootname [file tail $xci_file]] ; # file delete -force "$xci_file.out" # create_project -part $part_name -in_memory -ip ERROR: [Coretcl 2-106] Specified part could not be found. INFO: [Common 17-206] Exiting Vivado at Wed Aug 24 12:03:22 2016... Releasing IP location: /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma make[1]: *** [/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] Error 1 make[1]: Leaving directory `/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300' make: *** [X310_RFNOC_HGS] Error 2 -------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------------------------------------------- So I have a few questions: 1) I have the ten_gig_eth_pcs_pma ip core. But while opening a new xilinx project, I cannot find the part xc7k410tffg900-2 which seems to be because I dont have IP cores for Kintex 7. So how can I get IP cores for Kintex 7 which uses xc7k410tffg900-2 fpga? I only need the required licenses and not hardware support for Kintex 7. A link to just the licenses would be extremely helpful. 2) What are the other licenses I might need for writing my own computation engine for rfnoc_devel apart from the above? 3) I got a warning stating that I do not have the Vivado_HLS. I do not think that it is critical to the specific problem that I am having. But if it is so, can you suggest me a way to just get that part without garbling the installation? Thank You. Regards, Satrajit
JP
Jonathon Pendlum
Wed, Aug 24, 2016 2:18 PM

Hello Satrajit,

The rfnoc-devel branch is now using Vivado 2015.4. Run 'make cleanall' to
clear out all the old ip and build again.

  1. For the license, you need to go through Xilinx:
    http://www.xilinx.com/support/licensing_solution_center.html
  2. You do not need any other licenses.
  3. You can use Vivado HLS with RFNoC, but it is not required. Any warnings
    are due to the Xilinx setup scripts and can be ignored.

Jonathon

On Wed, Aug 24, 2016 at 5:26 AM, Mukherjee, Satrajit via USRP-users <
usrp-users@lists.ettus.com> wrote:

Hello,

I have a x310 type USRP and am currently working on the rfnoc-devel
branch. I have Xilinx Vivado 2015.2. After setting up the environment and

trying to make X310_RFNOC_HGS, I get the following error which is given
subsequently:

After that, I have a set of questions regarding the licenses I need.

This is what I get when I try to make:





rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ *source
setupenv.sh *
Setting up X3x0 FPGA build environment (64-bit)...
bash: /opt/Xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh:
No such file or directory

  • Vivado: Found (/opt/Xilinx/Vivado/2015.2/bin)

Environment successfully initialized.
rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ make
X310_RFNOC_HGS

make -f Makefile.x300.inc bin NAME=X310_RFNOC_HGS ARCH=kintex7
PART_ID=xc7k410t/ffg900/-2 ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1
NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16  RFNOC=1 X310=1
EXTRA_DEFS="ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1
SRAM_FIFO_SIZE=16  RFNOC=1 X310=1"
make[1]: Entering directory `/home/rfnoc/rfnoc/uhd/fpga-
src/usrp3/top/x300'
Vivado v2015.2 (64-bit)

---=======================
BUILDER: Building IP ten_gig_eth_pcs_pma

---=======================
BUILDER: Staging IP in build directory...
Reserving IP location:
/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma

BUILDER: Retargeting IP to part xc7k410tffg900-2...
BUILDER: Building IP...
*WARNING: Default location for XILINX_VIVADO_HLS not found: *

****** Vivado v2015.2 (64-bit)
**** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015
**** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/../tools/
scripts/viv_generate_ip.tcl

set xci_file        $::env(XCI_FILE)              ;

set part_name        $::env(PART_NAME)              ;

set gen_example_proj $::env(GEN_EXAMPLE)            ;

set synth_ip        $::env(SYNTH_IP)              ;

set ip_name [file rootname [file tail $xci_file]]  ;

file delete -force "$xci_file.out"

create_project -part $part_name -in_memory -ip

ERROR: [Coretcl 2-106] Specified part could not be found.
INFO: [Common 17-206] Exiting Vivado at Wed Aug 24 12:03:22 2016...
Releasing IP location: /home/rfnoc/rfnoc/uhd/fpga-
src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma
make[1]: ***
[/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out]
Error 1

make[1]: Leaving directory
`/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300'

make: *** [X310_RFNOC_HGS] Error 2







So I have a few questions:

  1. I have the ten_gig_eth_pcs_pma ip core. But while opening a new xilinx
    project, I cannot find the part

xc7k410tffg900-2 which seems to be because I dont have IP cores for Kintex
7. So how can I get IP cores for Kintex 7

which uses xc7k410tffg900-2 fpga? I only need the required licenses and
not hardware support for Kintex 7.

A link to just the licenses would be extremely helpful.

  1. What are the other licenses I might need for writing my own computation
    engine for rfnoc_devel apart from the above?

  2. I got a warning stating that I do not have the Vivado_HLS. I do not
    think that it is critical to the specific problem that

I am having. But if it is so, can you suggest me a way to just get that
part without garbling the installation?

                                                              Thank You.

Regards,

Satrajit


USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hello Satrajit, The rfnoc-devel branch is now using Vivado 2015.4. Run 'make cleanall' to clear out all the old ip and build again. 1) For the license, you need to go through Xilinx: http://www.xilinx.com/support/licensing_solution_center.html 2) You do not need any other licenses. 3) You can use Vivado HLS with RFNoC, but it is not required. Any warnings are due to the Xilinx setup scripts and can be ignored. Jonathon On Wed, Aug 24, 2016 at 5:26 AM, Mukherjee, Satrajit via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > > I have a x310 type USRP and am currently working on the rfnoc-devel > branch. I have Xilinx Vivado 2015.2. After setting up the environment and > > trying to make X310_RFNOC_HGS, I get the following error which is given > subsequently: > > After that, I have a set of questions regarding the licenses I need. > > > This is what I get when I try to make: > > > ------------------------------------------------------------ > ----------------------------------------------------------------- > > ------------------------------------------------------------ > ----------------------------------------------------------------- > > > rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ *source > setupenv.sh * > Setting up X3x0 FPGA build environment (64-bit)... > bash: */opt/Xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh: > No such file or directory* > - Vivado: Found (/opt/Xilinx/Vivado/2015.2/bin) > > *Environment successfully initialized.* > rfnoc@inets-ESPRIMO-P9003:~/rfnoc/uhd/fpga-src/usrp3/top/x300$ *make > X310_RFNOC_HGS* > make -f Makefile.x300.inc bin NAME=X310_RFNOC_HGS ARCH=kintex7 > PART_ID=xc7k410t/ffg900/-2 ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 > NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 RFNOC=1 X310=1 > EXTRA_DEFS="ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 > SRAM_FIFO_SIZE=16 RFNOC=1 X310=1" > make[1]: Entering directory `/home/rfnoc/rfnoc/uhd/fpga- > src/usrp3/top/x300' > Vivado v2015.2 (64-bit) > ======================================================== > BUILDER: Building IP ten_gig_eth_pcs_pma > ======================================================== > BUILDER: Staging IP in build directory... > *Reserving IP location: > /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma* > BUILDER: Retargeting IP to part xc7k410tffg900-2... > BUILDER: Building IP... > *WARNING: Default location for XILINX_VIVADO_HLS not found: * > > ****** Vivado v2015.2 (64-bit) > **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 > **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 > ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. > > source /home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/../tools/ > scripts/viv_generate_ip.tcl > # set xci_file $::env(XCI_FILE) ; > # set part_name $::env(PART_NAME) ; > # set gen_example_proj $::env(GEN_EXAMPLE) ; > # set synth_ip $::env(SYNTH_IP) ; > # set ip_name [file rootname [file tail $xci_file]] ; > # file delete -force "$xci_file.out" > # create_project -part $part_name -in_memory -ip > *ERROR: [Coretcl 2-106] Specified part could not be found.* > INFO: [Common 17-206] Exiting Vivado at Wed Aug 24 12:03:22 2016... > Releasing IP location: /home/rfnoc/rfnoc/uhd/fpga- > src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma > *make[1]: *** > [/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] > Error 1* > *make[1]: Leaving directory > `/home/rfnoc/rfnoc/uhd/fpga-src/usrp3/top/x300'* > *make: *** [X310_RFNOC_HGS] Error 2* > > > ------------------------------------------------------------ > ------------------------------------------------------------ > -------------------------------------------- > > ------------------------------------------------------------ > ------------------------------------------------------------ > --------------------------------------------- > > > So I have a few questions: > > > 1) I have the ten_gig_eth_pcs_pma ip core. But while opening a new xilinx > project, I cannot find the part > > xc7k410tffg900-2 which seems to be because I dont have IP cores for Kintex > 7. So how can I get IP cores for Kintex 7 > > which uses xc7k410tffg900-2 fpga? I only need the required licenses and > not hardware support for Kintex 7. > > A link to just the licenses would be extremely helpful. > > > 2) What are the other licenses I might need for writing my own computation > engine for rfnoc_devel apart from the above? > > > 3) I got a warning stating that I do not have the Vivado_HLS. I do not > think that it is critical to the specific problem that > > I am having. But if it is so, can you suggest me a way to just get that > part without garbling the installation? > > > Thank You. > > > Regards, > > Satrajit > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >