On Sun, 16 Sep 2018 23:06:06 +0200
Attila Kinali attila@kinali.ch wrote:
[2] "A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018
Oops.. I forgot to add the link to the pdf, sorry
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neal Stephenson
Hi
For moderate division ratios ( like 100 MHz down to 1 MHz ), the 20 log N stuff holds
pretty well ….
Bob
On Sep 17, 2018, at 12:37 AM, Dana Whitlow k8yumdoober@gmail.com wrote:
The act of squaring up the waveform alone might not do much harm, depending
on the extent
to which the phase noise on said waveform has already been filtered off.
But it's mainly when
the signal gets divided down by large ratios that the difference would
become really noticeable.
For example, take the case of 10 MHz starting frequency; the phase noise
several MHz out
is likely to be nil. But divide the 10 MHz down to, say, 1 Hz; then
there's likely to be quite a
lot of phase noise within "folding range" of many Nyquist bands about 1 Hz.
This, again, is why I wonder so much about our efforts in re-synthesizing
higher frequencies from
the 1PPS from GPS receivers. I don't know much the architecture of GPS
receivers, but it seems
to me it would sure be nice if there were some convenient way to extract a
clean signal at the
chipping rate, for use in generating standard reference frequencies.
Dana
On Sun, Sep 16, 2018 at 9:15 PM, Bob kb8tq kb8tq@n1k.org wrote:
Hi
It’s pretty easy to demonstrate that squaring up a sine wave, even with
fairly simple
circuits does not create crazy phase noise issues. People have been doing
it successfully
for a lot of years. In general faster saturated logic produces lower noise
floors than slower
logic.
Bob
On Sep 16, 2018, at 4:33 PM, Dana Whitlow k8yumdoober@gmail.com wrote:
I'd been thinking, in an admittedly non-rigorous sort of way, about this
matter for some years.
As I see it, it is certainly true that the phase of an oscillator's
output
is a continuous funciton
of time. It could be described as a continuous ramp, whose slope
corresponds to the frequency,
and with a little bit of non-flat random noise superimposed on it.
Now if you square up the waveform and do digital things with it (such as
freq dividing, digital
phase detection, etc), you are really only glimpsing the phase noise at
transition times, and
are blind in between. Thus the very process amounts to sampling the
phase
noise waveform
with a sampling phase detector. This view suggests that all the phase
noise power is aliased
and folded back into the band ranging from DC to Fsamp / 2, where Fsamp
is
the frequency
of the waveform after frequency division. This is why the time domain
jitter of the oscillator's
waveform is unchanged by "perfect" frequency division (or
multiplication).
It is why I wonder about the wisdom of doing phase comparison at
unnecessarily low frequency-
all that noise would seem to be scrunched down into a bandwidth of half
the
comparison frequency.
Does this explanation help, and how does it sit with those of you who
have
Moin,
On Sat, 15 Sep 2018 08:38:55 -0700
"Richard (Rick) Karlquist" richard@karlquist.com wrote:
On 9/15/2018 3:26 AM, Attila Kinali wrote:
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few
others
mentioned).
Wow, I never knew this in 45 years of designing synthesizers!
I do remember that some of the frequency counter engineers at HP
talked about noise aliasing. I think this is another way of
describing the same problem.
Yes. This effect has been known for a few decades at least.
What kind of puzzles me is, that I have not seen a mathematically
sound explanation of it, so far. People talk of aliasing and sampling,
but do not describe where the sampling happens in the first place.
After all, it's a time-continuous system and as such, there is no
sampling. One could look at it as a (sub-harmonic) mixing system,
but even that analogy falls short, as there is no second input.
It also fails at describing why there is not infinite energy being
down-mixed, as the resulting harmonic sum does not converge.
If someone knows of a description that goes beyond handwavy arguments,
I would very much appreciate hearing of them.
The only way to explain the effect in a rigorous way, that I could
figure out, is to apply Hajimiri and Lee's Impulse Sensitivity
Function[1],
and adapt from the oscillators they discribed to general periodic
systems.
(The step, as one can guess, is small, but hic sunt dracones)
Doing this, it becomes obvious that the down-mixing is an inherent
property of all systems that use or generate non-sinusoidal waveforms.
It is this ISF that is the source of the down-mixing/aliasing effect,
as it has a periodic waveform of sharp spikes.
As the ISF is probably (this is my intuition and I have, unfortunately,
no proof of this) related to the derivative of the produced output
waveform,
it becomes important to limit the slew rate of the output, to introduce
a second pole in the ISF and thus limit the number of harmonics.
Yet, it is also important to keep the input slew rate high, in order to
keep the width/height of the ISF pulses low.
A partial discussion of this can be found in the paper I presented
at IFCS earlier this year[2]. Unfortunately, the write-up is not
nice and I only realized after the deadline that I should have
all written it using a different approach. Sorry for that.
If something is not clear, do not hesitate to send me an email.
About 10 years ago, the frequency synthesizer chip vendors started
talking about a Figure of Merit (FOM) that predicted phase noise floor,
and it also included the 10 LOG N noise scaling. An application
engineer at ADI told me this was a characteristic of the sampling phase
detector that all these chips used. But I always wondered if the
frequency divider could come into play. The way FOM is defined,
it doesn't distinguish between phase detector and divider noise.
The 10*log(N) also applies to the phase detector in PLL chips,
where N becomes the ratio of the phase detector bandwidth divided
by the phase detector input frequency.
Given that the phase noise is dominated by the input source' phase
noise, there will be no appreciatable difference in whether the
down-mixing happens in the divider or the phase detector, as long
as the bandwidth of all components is the same. If the bandwidth
is different, we get into something akin Collins' zero crossing
detector[3] where appropriately designed stages with different
input bandwidths limit the energy that is down-mixed.
At Agilent, we used to make a lot of lab demos using a Centellax
(now Microsemi AKA Microchip) frequency divider that could divide by
any
number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
to divide down to 50 MHz. Now you have explained it.
Hmm? Are you implying those chips somehow were able to give
a 20*log(N) phase noise behaviour? If so, do you know how
they achieved such a feat?
If you divide by something that is not a power of 2, then it is
important
that each stage produces an output waveform with a 50% duty cycle.
Otherwise
flicker noise which has been up-mixed by a previous stage, will be
down-mixed
into the signal band, increasing the close-in phase-noise.
Wow, another thing I never knew.
I do not think that anyone was aware of this. A least I do not remember
seeing this being mentioned in any of the papers I have read. I, myself,
stumbled over it by accident. I was trying to design a sine-to-square
wave converter and wanted to understand what happend to the noise.
Especially the AM to PM conversion that a few people here have mentioned
a few times. I was looking at Claudio's measurement [4, page 28] and,
after applying Hajimir and Lee's ISF, I could (mathematically) explain
everything but what Enrico so nicely labled as "bump". None of the
explanations that I exchanged with Enrico, Claudio, Magnus and a few
other people made sense with the complete data. An external influence
didn't make sense as the flicker noise went from a straight ~6dB/oct
line
to a straight ~3db/oct line below 25MHz. This hunch got stronger when
Claudio shared the complete circuit they used with me(see figure 3 in
[2]).
The feedback circuit, which stabilizes duty cycle, has a -3dB frequency
of 0.28Hz, which is exactly the frequency where the bump is. And below
it, the flicker noise behavior seems to go back to approximately
6dB/oct.
For a complete explanation, see my paper[2] section 5.D "Scaling in a
Multi-Stage Sine-to-Square Converter."
The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%. Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.
I don't think the modulus prescaler is a good approach.
It will help reduce flicker noise, at the price of incrased
white noise, as the two division values will generate two
frequency spikes in the ISF that are close to each other.
There is probably some residual even harmonic content due to
the switching betwen the two scaler values, which will increase
flicker noise, not as much as having non-50% duty cycle, but still.
The right way to do it is to use both edges in case of odd division
factors (as some of the divider circuits by Linear/Analog seem to do).
Alternatively generate a ramp/sine output, ie use a Λ-divider
or a DDS, as both have much lower harmonics content in the ISF
and thus do not suffer from the down-mixing as much. If a square
waveform is required afterwards, a square-to-sine converter with
approriate bandwidth for the output frequency will solve that.
Attila Kinali
[1] "A General Theory of Phase Noise in Electrical Oscillators,"
by Hajimir and Lee, 1998
[2] "A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018
[3] "The Design of Low Jitter Hard Limiters," by Collins, 1996
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Hi Attila, everyone,
very interesting discussion!
People talk of aliasing and sampling,
but do not describe where the sampling happens in the first place.
After all, it's a time-continuous system and as such, there is no
sampling.
I would say that the sampling occurs when you're using only a slice of an
input signal. For instance, If you're using only the zero-crossing slice
of a sinewave to produce a divided version rather than the full envelope.
It's a matter of how you process information in your circuit.
"A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018
I read the paper, very interesting as well!
I have a minor remark, in the paper you relate the ISF (let's say
"sampling window") to the output slew rate of the comparator. I would say
that the sampling window should be related to the comparator input stage
bandwidth. If you have an high bandwidth input stage (e.g. 5 GHz) followed
by a slew rate limited output stage (e.g. 100 MHz) , high frequency noise
will trigger the output circuit and aliasing it. Viceversa, if you have a
low bandwidth input stage, even if the output stage is very fast, you don't
get input noise aliasing.
cheers
Mattia
Il giorno lun 17 set 2018 alle ore 13:46 Attila Kinali attila@kinali.ch
ha scritto:
On Sun, 16 Sep 2018 23:06:06 +0200
Attila Kinali attila@kinali.ch wrote:
[2] "A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018
Oops.. I forgot to add the link to the pdf, sorry
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neal Stephenson
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Attila Kinali writes:
Yes. This effect has been known for a few decades at least. What kind
of puzzles me is, that I have not seen a mathematically sound
explanation of it, so far.
I'm afraid I can't help with the rigor, but the fundamentals seem simple
enough to me.
People talk of aliasing and sampling, but do not describe where the
sampling happens in the first place. After all, it's a
time-continuous system and as such, there is no sampling.
That may be quibbling over terminology and definitions not actually
specified in those papers. Localization in the frequency domain
requires periodicity in the time domain (by definition) and moving
spectral features around can be done by convolution of the noise
spectrum with a localized signal (not necessarily of compact support,
but assume for the moment it is so you get a clearly defined pivot
frequency). That means you need to do multiplication in the time domain
with something periodic, so all you need to produce noise folding is for
instance a periodically varying NTF. I guess we can tick that box in
all instances you've mentioned.
One could look at it as a (sub-harmonic) mixing system, but
even that analogy falls short, as there is no second input.
Does it even matter if you call it a "second input"?
Reading the Egan paper I guess the line of arguments that leads to
"sampling", "mixing" and "aliasing" getting used is that the
periodically varying NTF (or ISF if you like) looks and acts
sufficiently like a Dirac comb that you can use sampling theory to
interpret the results. Or conversely, that you can take the results and
postulate a sampling process with a sampling aperture that happens to
look virtually identical to (one period of) your NTF. This seems not
much different than what gets routinely done when reasoning about
real-world systems that do "proper" sampling, but of course do not sport
a perfect dirac pulse sampling aperture.
It also fails at describing why there is not infinite energy being
down-mixed, as the resulting harmonic sum does not converge.
The actual integral or sum to compute would likely be governed by
something sinc-like, so convergence would eventually still happen with
any physically realizable input. That assumes you don't already need to
start with some generalization of the Fourier transform that has more
strictly defined convergence behaviour.
[…]
If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.
Wow, another thing I never knew.
I do not think that anyone was aware of this.
Funnily a paper I just read in TCAS-I (February 2017) by Pepe and
Andreani about phase noise in harmonic oscillators seems to mention this
(I think) as a known result w.r.t. flicker noise upconversion and
generalize (ref. eq. 90) on previous results for several particular
oscillator topologies which guarantee the necessary conditions. There
is also lots of discussion about the relation to the ISF and results in
conjunction with it that goes right above my head. The direction their
math is taking looks intriguing, so maybe you are able to glean
something from it to use. Whether there's any pre-existing link of
those results specifically to frequency dividers I don't know.
+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+
SD adaptations for KORG EX-800 and Poly-800MkII V0.9:
http://Synth.Stromeko.net/Downloads.html#KorgSDada
On Thu, 20 Sep 2018 23:45:27 +0200
Achim Gratz Stromeko@nexgo.de wrote:
Attila Kinali writes:
People talk of aliasing and sampling, but do not describe where the
sampling happens in the first place. After all, it's a
time-continuous system and as such, there is no sampling.
That may be quibbling over terminology and definitions not actually
specified in those papers. Localization in the frequency domain
requires periodicity in the time domain (by definition) and moving
spectral features around can be done by convolution of the noise
spectrum with a localized signal (not necessarily of compact support,
but assume for the moment it is so you get a clearly defined pivot
frequency). That means you need to do multiplication in the time domain
with something periodic, so all you need to produce noise folding is for
instance a periodically varying NTF. I guess we can tick that box in
all instances you've mentioned.
Exactly. But sofar nobody has properly specified what the other
term of the multiplication is.
One could look at it as a (sub-harmonic) mixing system, but
even that analogy falls short, as there is no second input.
Does it even matter if you call it a "second input"?
Not really, but if you want to argue about the noise folding
process as being a sub-harmonic mixing process, then you need
to specify what the second signal is that does the mixing.
Which in turn is again specifying the two terms of the multiplication
process as above.
It also fails at describing why there is not infinite energy being
down-mixed, as the resulting harmonic sum does not converge.
The actual integral or sum to compute would likely be governed by
something sinc-like, so convergence would eventually still happen with
any physically realizable input. That assumes you don't already need to
start with some generalization of the Fourier transform that has more
strictly defined convergence behaviour.
This is exactly one of the things that made me stumble when I first
went through the relevant literature. A sinc pulse-train in time
domain becomes a rectangular pulse-train in the frequency domain,
whose amplitude decays with 1/f. This means, the folded down noise
is a sum of terms decaying with 1/f. But this sum does not converge,
ie it goes to infinity. One has to add an addtional filter of some
sort that increases the rate of decay to 1/f^2 for the sum to converge.
Funnily a paper I just read in TCAS-I (February 2017) by Pepe and
Andreani about phase noise in harmonic oscillators seems to mention this
(I think) as a known result w.r.t. flicker noise upconversion and
Oh.. thanks! I somehow missed this paper. The results look indeed
interesting. But I have to spend some time to work through the math
in order to fully understand it.
Attila Kinali
--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes
Salut Mattia,
On Thu, 20 Sep 2018 12:31:01 +0200
Mattia Rizzi mattia.rizzi@gmail.com wrote:
People talk of aliasing and sampling,
but do not describe where the sampling happens in the first place.
After all, it's a time-continuous system and as such, there is no
sampling.
I would say that the sampling occurs when you're using only a slice of an
input signal. For instance, If you're using only the zero-crossing slice
of a sinewave to produce a divided version rather than the full envelope.
It's a matter of how you process information in your circuit.
Yes. That's the basic way how the sampling/noise-aliasing happens.
I just wonder why nobody (as far as I am aware of) has described
this process in detail. It looks obvious and if you look at the
general information theory/signal processing literature, it almost
falls out of the basic text books.
"A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018
I read the paper, very interesting as well!
I have a minor remark, in the paper you relate the ISF (let's say
"sampling window") to the output slew rate of the comparator. I would say
that the sampling window should be related to the comparator input stage
bandwidth. If you have an high bandwidth input stage (e.g. 5 GHz) followed
by a slew rate limited output stage (e.g. 100 MHz) , high frequency noise
will trigger the output circuit and aliasing it. Viceversa, if you have a
low bandwidth input stage, even if the output stage is very fast, you don't
get input noise aliasing.
Yes, exactly! Though, you have to look at a comparator IC as a multi-stage
system, where each gain-stage represents one "comparator" in my paper.
Hence the first gain stage already aliases the noise from its whole
bandwidth, which can be a lot of noise if the BW is large.
Hmm.. I probably should have made it more clear that the model I
defined applies only to single gain stages and not to whole components.
Attila Kinali
--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes
On Mon, 17 Sep 2018 00:37:43 -0500
Dana Whitlow k8yumdoober@gmail.com wrote:
For example, take the case of 10 MHz starting frequency; the phase noise
several MHz out
is likely to be nil. But divide the 10 MHz down to, say, 1 Hz; then
there's likely to be quite a
lot of phase noise within "folding range" of many Nyquist bands about 1 Hz.
For most low-noise systems, the white noise floor is dominated by
the thermal (Johnson) noise due to the 50 Ohm source impedance.
Although, one could say this noise is very low, it is wrong to
assume it can be ignored. Jitter, for a low-noise 10MHz system,
is dominated by the white noise and very little of the contribution
is due to flicker noise (unless you go for very long integration times).
This, again, is why I wonder so much about our efforts in re-synthesizing
higher frequencies from
the 1PPS from GPS receivers. I don't know much the architecture of GPS
receivers, but it seems
to me it would sure be nice if there were some convenient way to extract a
clean signal at the
chipping rate, for use in generating standard reference frequencies.
There are systems that do that, but one has to use signals from
multiple satellites to get the noise down. But for proper combination
of multiple signals one has to calculate a fix. Hence it is easier
to just check the reference oscillators phase against the fix.
And synthesizing from PPS is exactly this process of referencing
the 10MHz oscillator to the calculated fixes.
Attila Kinali
--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes
In message 20181010165425.df6d24aa3825ca765f301c0d@kinali.ch, Attila Kinali w
rites:
"A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018
[...]
Hence the first gain stage already aliases the noise from its whole
bandwidth, which can be a lot of noise if the BW is large.
Some years ago I spent a lot of time trying to find a way to
"oversample" single-shots of the 3rd zero-crossing of Loran-C
signals.
My finding was that of all the technologies available, the simple
comparator was the worst, because it only "looks" at a very tiny
time-slice around the actual zero-crossing, and thus is needlessly
sensitive to noise.
To make matters worse, the window is always late, it cannot be
symmetric, because at least some electrons have to move in the
opposite direction before the comparator changes state. HP has
interesting info about this in an old app-note on TI counters.
If the incoming curve-shape is unknown, that is the only thing one
can do, but when the curve-shape is known to be a sine or a loran-C,
better results can be had with a wider time window.
The final version of my code (This was SDR with an ADC directly on
the antenna) found the optimal least-square match between the sampled
signal and the theoretical signal for a configurable time-window,
produced the zero crossing from the theoretical signal.
Best performance was around 1/6-th period, which I'm sure there was
a reason for, but I gave up looking for it.
I have not found a way to implement it in the analog domain.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
How many samples of the Loran input signal in that 1/6th of the period?
On Wed, Oct 10, 2018 at 5:22 PM Poul-Henning Kamp phk@phk.freebsd.dk wrote:
In message 20181010165425.df6d24aa3825ca765f301c0d@kinali.ch, Attila Kinali w
rites:
"A Physical Sine-to-Square Converter Noise Model,"
by Kinali, 2018
[...]
Hence the first gain stage already aliases the noise from its whole
bandwidth, which can be a lot of noise if the BW is large.
Some years ago I spent a lot of time trying to find a way to
"oversample" single-shots of the 3rd zero-crossing of Loran-C
signals.
My finding was that of all the technologies available, the simple
comparator was the worst, because it only "looks" at a very tiny
time-slice around the actual zero-crossing, and thus is needlessly
sensitive to noise.
To make matters worse, the window is always late, it cannot be
symmetric, because at least some electrons have to move in the
opposite direction before the comparator changes state. HP has
interesting info about this in an old app-note on TI counters.
If the incoming curve-shape is unknown, that is the only thing one
can do, but when the curve-shape is known to be a sine or a loran-C,
better results can be had with a wider time window.
The final version of my code (This was SDR with an ADC directly on
the antenna) found the optimal least-square match between the sampled
signal and the theoretical signal for a configurable time-window,
produced the zero crossing from the theoretical signal.
Best performance was around 1/6-th period, which I'm sure there was
a reason for, but I gave up looking for it.
I have not found a way to implement it in the analog domain.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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In message CAPjwOuK90ncvoD1kkcSCmmVtCjGy2qNwt90tG=tau97zqcZ6dQ@mail.gmail.com
, Azelio Boriani writes:
How many samples of the Loran input signal in that 1/6th of the period?
Not many: At 5MHz sample rate it was 8 samples.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.