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View all threadsError while running command "rfnoc_image_builder -y ./e310_rfnoc_image_core.yml"
Hi everyone,
I am trying to run this command "rfnoc_image_builder -y
./e310_rfnoc_image_core.yml". I am getting plenty of warnings and 3 errors.
for complete terminal output I have also attached a file. Can any one help
me resolve this issue?
The errors are
ERROR: [Place 30-487] The packing of instances into the device could not be
obeyed. There are a total of 13300 slices in the device, of which 9737
slices are available, however, the unplaced instances require 10808 slices.
Please analyze your design to determine if the number of LUTs, FFs, and/or
control sets can be reduced.
ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed
please check previous errors for details.'
ERROR: [Common 17-69] Command failed: Placer could not place all instances
[00:13:44] Current task: Placer +++ Current Phase: 3.6 Small Shape Detail
Placement
[00:13:45] Current task: Placer +++ Current Phase: Finished
[00:13:45] Process terminated. Status: Failure
Hi Muhammad,
It says the design doesn't fit in the FPGA. Did you modify the YAML or FPGA
code? If so, you may need to reduce what you're including. If not, maybe
try building the unmodified FPGA:
cd fpga/usrp3/top/e31x
source setupenv.sh
make E310_SG3
Thanks,
Wade
On Tue, Dec 12, 2023 at 9:05 AM Muhammad Hassan engr.muhd.hassan@gmail.com
wrote:
Hi everyone,
I am trying to run this command "rfnoc_image_builder -y
./e310_rfnoc_image_core.yml". I am getting plenty of warnings and 3 errors.
for complete terminal output I have also attached a file. Can any one help
me resolve this issue?
The errors are
ERROR: [Place 30-487] The packing of instances into the device could not
be obeyed. There are a total of 13300 slices in the device, of which 9737
slices are available, however, the unplaced instances require 10808 slices.
Please analyze your design to determine if the number of LUTs, FFs, and/or
control sets can be reduced.
ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed
please check previous errors for details.'
ERROR: [Common 17-69] Command failed: Placer could not place all instances
[00:13:44] Current task: Placer +++ Current Phase: 3.6 Small Shape Detail
Placement
[00:13:45] Current task: Placer +++ Current Phase: Finished
[00:13:45] Process terminated. Status: Failure
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Dear Wade,
Thank you very much for your response. The YAML was modified by ettus research (Jonathon). He added replay block and sent me via email. I replaced that file in following folder (uhd/fpga/usrp3/top/e31x) and then run command. I also installed vivado 2021.1 according to his instructions
The E310 has a very small FPGA, so fitting the replay block and DRAM logic
is a challenge. You might be able to fit a single replay channel, but
nothing else extra. If you're limiting the device to one channel, you might
also be able to remove one of the radio channels and the corresponding
stream endpoint to free up some space.
Wade
On Tue, Dec 12, 2023 at 10:12 AM engr.muhd.hassan@gmail.com wrote:
Dear Wade,
Thank you very much for your response. The YAML was modified by ettus
research (Jonathon). He added replay block and sent me via email. I
replaced that file in following folder (uhd/fpga/usrp3/top/e31x) and then
run command. I also installed vivado 2021.1 according to his instructions
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Could you please tell me how can solve this issue? As I am using GNU radio, when I increase sample rate beyond 2MS/s it misses samples. So, Ettus suggested me to use RFNoC replay Block. They also provided me with YAML file. I have two E313 USRPs and I have to use them for outdoor channel modelling. Could you please help me with that?
A while back, I built an E310 image using "static" linking. This allowed me
to include a 2 channel replay block with a 2 channel radio. The yml may
require an update or two to work with the current UHD version, but see if
you can build an image with static links. Keep in mind that with static
links you will be forced to use the replay block since you will not be able
to dynamically bypass it.
Rob
On Tue, Dec 12, 2023 at 1:55 PM engr.muhd.hassan@gmail.com wrote:
Could you please tell me how can solve this issue? As I am using GNU
radio, when I increase sample rate beyond 2MS/s it misses samples. So,
Ettus suggested me to use RFNoC replay Block. They also provided me with
YAML file. I have two E313 USRPs and I have to use them for outdoor channel
modelling. Could you please help me with that?
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Wade,
With current versions of the replay block supporting a FIFO mode, is there
any reason why Ettus does not include a statically linked Replay block as
part of the default image for the E310?
Rob
On Tue, Dec 12, 2023 at 2:18 PM Rob Kossler rkossler@nd.edu wrote:
A while back, I built an E310 image using "static" linking. This allowed
me to include a 2 channel replay block with a 2 channel radio. The yml may
require an update or two to work with the current UHD version, but see if
you can build an image with static links. Keep in mind that with static
links you will be forced to use the replay block since you will not be able
to dynamically bypass it.
Rob
On Tue, Dec 12, 2023 at 1:55 PM engr.muhd.hassan@gmail.com wrote:
Could you please tell me how can solve this issue? As I am using GNU
radio, when I increase sample rate beyond 2MS/s it misses samples. So,
Ettus suggested me to use RFNoC replay Block. They also provided me with
YAML file. I have two E313 USRPs and I have to use them for outdoor channel
modelling. Could you please help me with that?
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Hi Wade & Rob,
Thank you for your help.
I am a new user, so I do not know much about Linux and FPGA. My aim is to use my usrp with high sampling rate so I was recommended to use RFNoC replay block. For this purpose, I received YML file from Ettus (from Jonathon). I replaced that file (e310_rfnoc_image_core.yml) with the already existing file to the location (/uhd/fpga/usrp3/top/e31x) and from this folder I executed the command “rfnoc_image_builder -y
./e310_rfnoc_image_core.yml “.
I am not sure whether I did it correctly or not.
regards
Hassan
Dear Wade,
I also executed following commands as you suggested. I have also attached full log file.
cd fpga/usrp3/top/e31x
source setupenv.sh
make E310_SG3
Following is the result
00:17:25] Current task: Write Bitstream +++ Current Phase: Starting
[00:17:26] Current task: Write Bitstream +++ Current Phase: Finished
[00:17:26] Process terminated. Status: Success
---=======================
Warnings: 1069
Critical Warnings: 125
Errors: 0
make[1]: Leaving directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x'
Exporting bitstream file...
Exporting build report...
Build DONE ... E310_SG3