Having difficulty creating a project to actually test out the N310 HG design. (I am having problems with a no-Os setup that I am trying to execute to find out what exactly the pin assignment should be for the MIOs. On a side note, the issue specifically is wrt I2C0, USB and TPM pin assignments. Schematics vs PS7 design does not seem to match up. Ettus support email from about a month ago stated schematic is right but now I am having second thoughts about it) Usually, when working with ettus products, I generate, using ettus' script with GUI=1, a project, which afterwards I save to make a tcl script for a project to impl and resynthesize it as my own project. Through this process, (mind you i have not gotten to regenerating a tcl script yet) (and this was a relatively easy fix), the custom packaged ips were not found and I had to insert them from (vivado_ipi) folder. Design went through synthesis fine. At implementation, though, I am seeing this error: (sub-design 'n310_ps_bd.bd is not generated for Synthesis target. Please open this sub-design and generate with synth_checkpoint_mode as signular in original project before adding it to current project' [image: Selection_062.bmp] I have made sure to get the ip report status, all ips are not locked. I have tried to search for answers online but nothing seems to pop up. Anyone has encountered this problem?

https://www.xilinx.com/support/answers/68238.html. This pretty much is the issue. On Fri, Oct 18, 2019 at 11:13 AM Samuel Berhanu <samberhanu@gmail.com> wrote: > Having difficulty creating a project to actually test out the N310 HG > design. (I am having problems with a no-Os setup that I am trying to > execute to find out what exactly the pin assignment should be for the MIOs. > On a side note, the issue specifically is wrt I2C0, USB and TPM pin > assignments. Schematics vs PS7 design does not seem to match up. Ettus > support email from about a month ago stated schematic is right but now I am > having second thoughts about it) > > Usually, when working with ettus products, I generate, using ettus' script > with GUI=1, a project, which afterwards I save to make a tcl script for a > project to impl and resynthesize it as my own project. > > Through this process, (mind you i have not gotten to regenerating a tcl > script yet) (and this was a relatively easy fix), the custom packaged ips > were not found and I had to insert them from (vivado_ipi) folder. > > Design went through synthesis fine. At implementation, though, I am > seeing this error: > (sub-design 'n310_ps_bd.bd is not generated for Synthesis target. Please > open this sub-design and generate with synth_checkpoint_mode as signular in > original project before adding it to current project' > > [image: Selection_062.bmp] > > I have made sure to get the ip report status, all ips are not locked. > > I have tried to search for answers online but nothing seems to pop up. > Anyone has encountered this problem? >

What version of Vivado are you using? For some reason, the manual on the Ettus website is for UHD version 3.15.0.0-69-gc350eb5a6, which requires 2018.3 and is not actually an official release. If memory serves, the actual tagged release (v.3.14.1.1) requires Vivado 2017.4. I've definitely created Vivado projects for the N310 with GUI=1...with Vivado 2017.4. Also, I don't think the schematic is actually correct, for the record. -Robin On Fri, Oct 18, 2019 at 8:33 AM Samuel Berhanu via USRP-users < usrp-users@lists.ettus.com> wrote: > https://www.xilinx.com/support/answers/68238.html. This pretty much is > the issue. > > > On Fri, Oct 18, 2019 at 11:13 AM Samuel Berhanu <samberhanu@gmail.com> > wrote: > >> Having difficulty creating a project to actually test out the N310 HG >> design. (I am having problems with a no-Os setup that I am trying to >> execute to find out what exactly the pin assignment should be for the MIOs. >> On a side note, the issue specifically is wrt I2C0, USB and TPM pin >> assignments. Schematics vs PS7 design does not seem to match up. Ettus >> support email from about a month ago stated schematic is right but now I am >> having second thoughts about it) >> >> Usually, when working with ettus products, I generate, using ettus' >> script with GUI=1, a project, which afterwards I save to make a tcl >> script for a project to impl and resynthesize it as my own project. >> >> Through this process, (mind you i have not gotten to regenerating a tcl >> script yet) (and this was a relatively easy fix), the custom packaged ips >> were not found and I had to insert them from (vivado_ipi) folder. >> >> Design went through synthesis fine. At implementation, though, I am >> seeing this error: >> (sub-design 'n310_ps_bd.bd is not generated for Synthesis target. Please >> open this sub-design and generate with synth_checkpoint_mode as signular in >> original project before adding it to current project' >> >> [image: Selection_062.bmp] >> >> I have made sure to get the ip report status, all ips are not locked. >> >> I have tried to search for answers online but nothing seems to pop up. >> Anyone has encountered this problem? >> > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

I just checked the repo based on the tag you mentioned and it is indeed 2017.4 (based on its setupenv.sh) https://github.com/EttusResearch/fpga/blob/bb85bdff45cad4da5008ab0c58749ce32797cea7/usrp3/top/n3xx/setupenv.sh ________________________________ From: USRP-users <usrp-users-bounces@lists.ettus.com> on behalf of Robin Coxe via USRP-users <usrp-users@lists.ettus.com> Sent: Friday, October 18, 2019 11:59 AM To: Samuel Berhanu <samberhanu@gmail.com> Cc: Ettus Mail List <usrp-users@lists.ettus.com> Subject: Re: [USRP-users] N310 generation of a project/bit file from Ettus design (HG version) What version of Vivado are you using? For some reason, the manual on the Ettus website is for UHD version 3.15.0.0-69-gc350eb5a6, which requires 2018.3 and is not actually an official release. If memory serves, the actual tagged release (v.3.14.1.1) requires Vivado 2017.4. I've definitely created Vivado projects for the N310 with GUI=1...with Vivado 2017.4. Also, I don't think the schematic is actually correct, for the record. -Robin On Fri, Oct 18, 2019 at 8:33 AM Samuel Berhanu via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: https://www.xilinx.com/support/answers/68238.html<https://urldefense.proofpoint.com/v2/url?u=https-3A__www.xilinx.com_support_answers_68238.html&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=W_MQLyUWPXWHfsF4mr51mTMqpeO4RbBBLexficV9DG8&m=3eiW44eEXen8sH4bvJLonsYOrBQlSZTtEN1f0476lHE&s=-27ilFCQOwzFKD4xO7v0coUAB_WM_p_lm9RF391SBe4&e=>. This pretty much is the issue. On Fri, Oct 18, 2019 at 11:13 AM Samuel Berhanu <samberhanu@gmail.com<mailto:samberhanu@gmail.com>> wrote: Having difficulty creating a project to actually test out the N310 HG design. (I am having problems with a no-Os setup that I am trying to execute to find out what exactly the pin assignment should be for the MIOs. On a side note, the issue specifically is wrt I2C0, USB and TPM pin assignments. Schematics vs PS7 design does not seem to match up. Ettus support email from about a month ago stated schematic is right but now I am having second thoughts about it) Usually, when working with ettus products, I generate, using ettus' script with GUI=1, a project, which afterwards I save to make a tcl script for a project to impl and resynthesize it as my own project. Through this process, (mind you i have not gotten to regenerating a tcl script yet) (and this was a relatively easy fix), the custom packaged ips were not found and I had to insert them from (vivado_ipi) folder. Design went through synthesis fine. At implementation, though, I am seeing this error: (sub-design 'n310_ps_bd.bd<https://urldefense.proofpoint.com/v2/url?u=http-3A__n310-5Fps-5Fbd.bd&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=W_MQLyUWPXWHfsF4mr51mTMqpeO4RbBBLexficV9DG8&m=3eiW44eEXen8sH4bvJLonsYOrBQlSZTtEN1f0476lHE&s=v_uR1v1M6qpcMcrnOG4j6n9EfYEJR0E78MOBZDPHgvM&e=> is not generated for Synthesis target. Please open this sub-design and generate with synth_checkpoint_mode as signular in original project before adding it to current project' [Selection_062.bmp] I have made sure to get the ip report status, all ips are not locked. I have tried to search for answers online but nothing seems to pop up. Anyone has encountered this problem? _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com<https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.ettus.com_mailman_listinfo_usrp-2Dusers-5Flists.ettus.com&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=W_MQLyUWPXWHfsF4mr51mTMqpeO4RbBBLexficV9DG8&m=3eiW44eEXen8sH4bvJLonsYOrBQlSZTtEN1f0476lHE&s=OoJK6KBq8fqrN-m5Sj3kVA77pT_-zkwp3z52c-wWf3o&e=>

Hi all, As Jason mentioned, UHD 3.14.x uses Vivado 2017.4. UHD 3.15.x.x which will be released soon bumps the Vivado dep to 2018.3. The current manual at uhd.ettus.com is built off the master branch, so it's a bit ahead of the release at the moment. We are working on adding in an archive of all previously tagged manuals so they will be easily accessible for reference. Note, when building UHD, the manual (for your version) is installed at $INSTALL_PREFIX/share/doc/uhd/doxygen/html Regards, Nate Temple On Fri, Oct 18, 2019 at 10:03 AM Jason Matusiak via USRP-users < usrp-users@lists.ettus.com> wrote: > I just checked the repo based on the tag you mentioned and it is indeed > 2017.4 (based on its setupenv.sh) > > > https://github.com/EttusResearch/fpga/blob/bb85bdff45cad4da5008ab0c58749ce32797cea7/usrp3/top/n3xx/setupenv.sh > > ------------------------------ > *From:* USRP-users <usrp-users-bounces@lists.ettus.com> on behalf of > Robin Coxe via USRP-users <usrp-users@lists.ettus.com> > *Sent:* Friday, October 18, 2019 11:59 AM > *To:* Samuel Berhanu <samberhanu@gmail.com> > *Cc:* Ettus Mail List <usrp-users@lists.ettus.com> > *Subject:* Re: [USRP-users] N310 generation of a project/bit file from > Ettus design (HG version) > > What version of Vivado are you using? > For some reason, the manual on the Ettus website is for UHD version > 3.15.0.0-69-gc350eb5a6, which requires 2018.3 and is not actually an > official release. > If memory serves, the actual tagged release (v.3.14.1.1) requires Vivado > 2017.4. > > I've definitely created Vivado projects for the N310 with GUI=1...with > Vivado 2017.4. Also, I don't think the schematic is actually correct, for > the record. > > -Robin > > On Fri, Oct 18, 2019 at 8:33 AM Samuel Berhanu via USRP-users < > usrp-users@lists.ettus.com> wrote: > > https://www.xilinx.com/support/answers/68238.html > <https://urldefense.proofpoint.com/v2/url?u=https-3A__www.xilinx.com_support_answers_68238.html&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=W_MQLyUWPXWHfsF4mr51mTMqpeO4RbBBLexficV9DG8&m=3eiW44eEXen8sH4bvJLonsYOrBQlSZTtEN1f0476lHE&s=-27ilFCQOwzFKD4xO7v0coUAB_WM_p_lm9RF391SBe4&e=>. > This pretty much is the issue. > > > On Fri, Oct 18, 2019 at 11:13 AM Samuel Berhanu <samberhanu@gmail.com> > wrote: > > Having difficulty creating a project to actually test out the N310 HG > design. (I am having problems with a no-Os setup that I am trying to > execute to find out what exactly the pin assignment should be for the MIOs. > On a side note, the issue specifically is wrt I2C0, USB and TPM pin > assignments. Schematics vs PS7 design does not seem to match up. Ettus > support email from about a month ago stated schematic is right but now I am > having second thoughts about it) > > Usually, when working with ettus products, I generate, using ettus' script > with GUI=1, a project, which afterwards I save to make a tcl script for a > project to impl and resynthesize it as my own project. > > Through this process, (mind you i have not gotten to regenerating a tcl > script yet) (and this was a relatively easy fix), the custom packaged ips > were not found and I had to insert them from (vivado_ipi) folder. > > Design went through synthesis fine. At implementation, though, I am > seeing this error: > (sub-design 'n310_ps_bd.bd > <https://urldefense.proofpoint.com/v2/url?u=http-3A__n310-5Fps-5Fbd.bd&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=W_MQLyUWPXWHfsF4mr51mTMqpeO4RbBBLexficV9DG8&m=3eiW44eEXen8sH4bvJLonsYOrBQlSZTtEN1f0476lHE&s=v_uR1v1M6qpcMcrnOG4j6n9EfYEJR0E78MOBZDPHgvM&e=> > is not generated for Synthesis target. Please open this sub-design and > generate with synth_checkpoint_mode as signular in original project before > adding it to current project' > > [image: Selection_062.bmp] > > I have made sure to get the ip report status, all ips are not locked. > > I have tried to search for answers online but nothing seems to pop up. > Anyone has encountered this problem? > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > <https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.ettus.com_mailman_listinfo_usrp-2Dusers-5Flists.ettus.com&d=DwMFaQ&c=euGZstcaTDllvimEN8b7jXrwqOf-v5A_CdpgnVfiiMM&r=W_MQLyUWPXWHfsF4mr51mTMqpeO4RbBBLexficV9DG8&m=3eiW44eEXen8sH4bvJLonsYOrBQlSZTtEN1f0476lHE&s=OoJK6KBq8fqrN-m5Sj3kVA77pT_-zkwp3z52c-wWf3o&e=> > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >