On 22.08.22 00:24, John Sloan via time-nuts wrote:

Sparkfun's ZED-F9T breakout board interfaces look like a step up from
u-blox' RCB-F9T. However, my reason to use the RCB-F9T is simple: I've
had a bunch of these for years and don't want to throw them away. Also,
I need to feed the timepulse signals into a 50 Ohm load and the ZED-F9T
output pins are only rated for max. 5 mA [1]. Except for a 33 Ohm
resistor, the Sparkfun board routes both timepulse pins directly to the
SMA connectors [2]. I doubt that results in 50 Ohm source impedance
required to properly drive a high impedance load via a 50 Ohm
transmission line.

Have you had any issues with unmatched transmission line effects?

Best regards,
Carsten

[1]
https://content.u-blox.com/sites/default/files/ZED-F9T-00B_DataSheet_UBX-18053713.pdf#page=13
[2]
https://cdn.sparkfun.com/assets/6/c/2/5/b/SparkFun_GNSS_Timing-ZED-F9T_Schematic.pdf

Hi

The issue of terminating PPS signals and how to do it “right” has been debated
a lot on this list. A quick summary:

1. Some sort of termination is a really good idea. That termination should match
   the coax being used.

2. Some devices you might wish to drive already have a 50 ohm termination in
   them.

3. Most “modern” devices expect you to hit some sort of logic level with your
   drive signal. Is that 50% of 5V, 3.3V, 2.5V? Is it 0.8V TTL? Unfortunately each
   device and design is a bit different.

4. Will your “gizmo” that is looking for 3.3V ( or worse 2.5V) logic be ok with a
   5V peak signal? One would hope it will. There are some examples where the
   answer is no …

So what to do?

1. If you terminate with 50 ohms at the source, you can drive unterminated
   loads pretty well. Logic levels tend to line up. “Un-terminating” pieces of commercial
   gear simply to allow a terminated drive might not be a fun thing.

2. You can terminate both ends of the coax. This makes for the best match
   and the least ring on the line. It also means quite a bit of drive current. If you want
   5V logic levels, you need 10V drive. Good luck with your 3.3V unterminated device
   plugged into that output by accident ….

3. You can just terminate the load and drive the line from a low impedance / high
   current driver. Hitting a full ( so 90% ) logic swing this way at 5V into a load termination
   takes a pretty hefty driver. It also has to be fast and low jitter. Unfortunately this is
   what a lot of commercial gear seems to expect you to do.

If you have control over all the sources and loads, then picking a logic voltage is the
first step. Assuming there is a common ground, power all the sources with that
voltage. Make sure all the loads can tolerate / accept that voltage. Source only
50 ohm termination likely would be the rational way to set things up.

One can get “buffer” rated logic gates. Be sure to check things like the package
dissipation / current before buying a SOT-23 sized gizmo with 8 gates in it ( and
good luck mounting that BGA part … yikes …). Yes the duty cycle is low with
1 us pulses. Not so much with 50% duty cycle. Either way, package current may
limit you.

Parallel up as many gates as needed to hit the required current. If you are source
terminating a source load resistor goes in series with each gate output. With load
only termination, very small resistors are typically used (or no resistors at all). To hit
full 5V logic into load only terminated 50 ohms, you will use a lot of gates ….

Fun !!

Bob

Hi Folks,

read carefully ITU G.703 for 1PPS 50 Ohm or v.11 interface on RJ45 Con.

Cheers.

Uwe

Gesendet mit der mobilen Mail App

Am 22.08.22 um 20:47 schrieb Bob kb8tq via time-nuts

Hi Bob, Uwe,

thanks for the extensive summary and the ITU G.703 reference!

As an RF engineer by profession, I'm compelled to not (knowingly)
mistreat transmission lines :D

3.3V LVCMOS output level is determined by the ZED-F9T, so the
straightforward solution was to add a hand-solderable buffer opamp (TI
BUF602) that can drive +17 dBm into a 50 Ohm load. +17 dBm is already
quite a strong signal for most 50 Ohm RF measurement gear, so another
reason for being able to drive 50 Ohm loads is the option to use
standard 50 Ohm attenuators. Alternatively, the buffer amp enables 50
Ohm source termination to reliably drive 3.3V into high-impedance loads.
A good coincidence that the resulting output levels are ITU G.703
compliant :)

Best regards,
Carsten

On 22.08.22 21:00, Uwe via time-nuts wrote:

Hi

The BUF 602 needs dual 5V supplies to hit 3.3V logic levels. Running multiple supplies is a
bit of a PIA. Since this is a logic signal, cheap / fast / stable logic gates would seem to be
the obvious way to get the job done. 3.3V supply and away you go … The usual suspects
are all at least as fast and at least as low jitter as the BUF 602.

Bob

Hi Bob,

On 24.08.22 04:20, Bob kb8tq wrote:

I initially thought the same about the dual supplies. Fortunately, the
required average currents are fairly low (<100 mA to drive 5 loads at
3.3V and 50 Ohm each), so an inverting charge pump will do the job. The
SOT-23 LM2776 requires 3 capacitors in external circuitry, the WSON
LM27761 needs 4 caps and 2 resistors. I'm using the LM27761 on my
RCB-F9T adapter board. See my initial post for the layout.

Can you point me to any measurements or data sheets that characterize
the rise time, temperature dependency, and/or jitter/phase noise
performance of suitable logic gates? The fastest device families I could
find are 74LVC, 74AVC, and 74AUC. The 74HC often relied upon are
actually very slow [1]. I've discussed using 74-type components on the
EEVblog forum [2]. The 74s' typically large temperature coefficient
alone makes me reluctant to use them. The lack of jitter specs is an
exclusion criterion for me.

What are the "usual suspects" you refer to? I couldn't find any 74ish
device with official specs that can compete with the BUF602. As a
reasonably linear analog buffer, it shouldn't add any jitter on top of
its input voltage noise and has >45 dB PSRR up to 1 MHz. Its 8 V/ns slew
rate enables <0.5 ns rise times and it is straightforward to achieve 50
Ohm source termination. Improper source termination is also an exclusion
criterion for me.

In comparison, logic gates don't spec rise times <1 ns, have presumably
– correct me if I'm wrong – negligible PSRR, don't specify output
impedance, and require paralleling multiple outputs to drive 50 Ohm loads.

While the use of 74s may work for my application (whether sub-optimal or
not would be subject to tests), I'd rather err on the side of caution by
using parts that are explicitly specified for my use case.

Best regards,
Carsten

P.S.: If you're wondering why I need such high slew rates, my
application is phase synchronization of RF synthesizers like TI's
LMX2594. These require low phase noise, high slew rate reference and
sync signals. Again, I prefer to err on the side of caution by providing
the highest slew rate I can realize with reasonable effort.

[1] https://www.ti.com/lit/sg/sdyu001ab/sdyu001ab.pdf#page=2
[2]
https://www.eevblog.com/forum/projects/gpsdognssdo-stm32g4-u-blox-zed-f9t-tdc7200/msg4357849/#msg4357849

Carsten,
Forgive me asking an uninformed question
The LM27761 switches at 2MHz and is claimed to be low noise as the
switching is so fast but I expect it radiates at 2MHz and all harmonics.
You are looking for a 1ns rise time, probably to avoid diluting the 1PPS
accuracy, so the moment the 1PPS signal causes the line driver to switch
must be very well determined and stable
How do you avoid these harmonics to interfere with this switching?
I'm asking because I'm experiencing some problems with leakage of a
10MHz clock into the input of a fast comparator used for edge detection
and input to a counter, both on the same PCB, so I hope to learn from you.
Erik.

On 24-8-2022 9:19, Carsten Andrich via time-nuts wrote:

I don't see any explicit jitter specs on the BUF602 datasheet either.
Have you measured it?
How consistent is it from part to part?
The jitter of most CMOS families has been measured.
For example 74HC buffers typically have ~4ps jitter at room temperature.
Even this is much lower than the jitter of typical FPGAs when the effect of cross coupling from other clock domains such as internal oscillators etc are taken into account.
Faster logic families such as 74AC buffers (~ 1ps) have even lower jitter.
CMOS devices have a typical propagation delay tempco of around 0.4% of the delay per/C. FPGA gates have similar delay tempcos.
Neither the delay tempco nor the jitter is typically specified on CMOS device datasheets nor are they on the BUF602 datasheet so you have to measure them or leverage the results obtained by others.

Bruce

Am 2022-08-24 9:19, schrieb Carsten Andrich via time-nuts:

LMX2594 should not be very time pressing. I have published an
article in Dubus early this year on LMX2594 and everyone asked me then
where to buy.
I got 2 from Digikey last winter and since then the delivery time
was 1 year, and keeps being a year. :-(

Gerhard