Re: [time-nuts] Linear Interpolator
Magnus,
Regarding your suggested discrete solution (viz. current mirror, ADC, etc):
Will it be relatively easy to achieve 1ns resolution and a range of say
100ns (for 10MHz) with sub-nanosecond accuracy?
Regards,
Stephan Sandenbergh
From: "Stephan Sandenbergh" stephan@rrsg.ee.uct.ac.za
Subject: Re: [time-nuts] Linear Interpolator
Date: Thu, 29 Jun 2006 11:42:16 +0200
Message-ID: 000901c69b60$4eea6e30$401c9e89@Stephan
Magnus,
Stephan,
Regarding your suggested discrete solution (viz. current mirror, ADC, etc):
Will it be relatively easy to achieve 1ns resolution and a range of say
100ns (for 10MHz) with sub-nanosecond accuracy?
Well, go and look in the HP5335A service manual and decide for yourself.
Naturally, there is the issue about input/trigger design, but that is a common
problem.
I would not do this stuff with a clock lower than 50 MHz today. It is easy
enought to acomplish it. 10 MHz is nice and dandy for reference, but I would
use a low-jitter VCXO and lock it to the 10 MHz and then use that clock for
measurements.
Cheers,
Magnus
[Magnus Danielson wrote :
I would not do this stuff with a clock lower than 50 MHz today. It is easy
enought to acomplish it. 10 MHz is nice and dandy for reference, but I would
use a low-jitter VCXO and lock it to the 10 MHz and then use that clock for
measurements.]
Hi,
So you suggest, I take the 10MHz output of my OCXO lock that to a stable
VCXO (say 64MHz as not to be a harmonic multiple of 10MHz) and then clock my
FPGA with the resultant output. Wouldn't I loose the advantage of the
dithering effect? I guess if I have a 1ns resolution interpolator, no
dithering is needed? Is the idea to have a sort of a loop within a loop -
the FPGA follows the OCXO which follows the 1PPS?
Regards,
Stephan.
From: "Stephan Sandenbergh" stephan@rrsg.ee.uct.ac.za
Subject: Re: [time-nuts] Linear Interpolator
Date: Thu, 29 Jun 2006 13:58:06 +0200
Message-ID: 000d01c69b73$489311a0$401c9e89@Stephan
[Magnus Danielson wrote :
I would not do this stuff with a clock lower than 50 MHz today. It is easy
enought to acomplish it. 10 MHz is nice and dandy for reference, but I would
use a low-jitter VCXO and lock it to the 10 MHz and then use that clock for
measurements.]
Hi,
So you suggest, I take the 10MHz output of my OCXO lock that to a stable
VCXO (say 64MHz as not to be a harmonic multiple of 10MHz) and then clock my
FPGA with the resultant output.
I would rephrase that to say that you should lock your low jitter VCXO (of say
64 MHz) to your stable OCXO (of 10 MHz).
Highest common frequency is 2 MHz (divide by 5 for 10 MHz and divide by 32 for
64 MHz). Apply suitable phase-comparator and loop filter of choice.
What you said could be interprented as locking the 10 MHz OCXO to the 64 MHz
clock, which would be slaving the wrong oscillator of the two.
Wouldn't I loose the advantage of the dithering effect? I guess if I have a
1ns resolution interpolator, no dithering is needed?
Indeed. Instead of averaging out the difference, you get improved single-shot
resolution and have less measurement error noise to clog your other
measurements. Sawtooth-corrections will then certainly be needed to combat the
resolution problem of the PPS itself.
Is the idea to have a sort of a loop within a loop -
the FPGA follows the OCXO which follows the 1PPS?
Eh, I didn't say that (I kept my mind in the measurement side of the system),
but you can do that if you want. It will be pretty straight-forward. Update a
DAC to stabilize the OCXO just to keep the balance of the time interval
readings. The time interval measurements is the phase-detector, so loop-filter
needs to be applied accordingly.
Oh, what 64 MHz oscillator do you have?
Cheers,
Magnus
Hi,
So you suggest, I take the 10MHz output of my OCXO lock that to a stable
VCXO (say 64MHz as not to be a harmonic multiple of 10MHz) and then clock
my FPGA with the resultant output.
I would rephrase that to say that you should lock your low jitter VCXO (of
say 64 MHz) to your stable OCXO (of 10 MHz).
Thanks for correcting me. This is actually what I meant.
Oh, what 64 MHz oscillator do you have?
Currently I don't have a 64MHz VCO yet. I'm just weighing my options. My
original idea was too run the FPGA off a 64MHz free-running XO. This would
have given me 15.6ns resolution with a simple start-stop type phase detector
(and not too much EMI problems). However, in retrospect, I doubt if that
will give me the 1ns dithered accuracy I want. It will be a shame to add
substantial noise to the low 2ns jitter of the M12+T. I guess the final
dithered accuracy depends on one's pre-averaging time.
Well, I still think it might be better to run off a free-running XO to have
the dithering advantage. My application requires good stability (ideally sub
ns) between distant locations (maybe in the order of 100s of meters to 10s
of kilometres) on time scales of 100s of seconds to a few minutes.
I guess one can view the PLL as a very sharp roll-off low-pass filter. If
one could have less jitter (via sawtooth correction and a good resolution
phase detector) at the 1PPS input in the first place, one could set your PLL
bandwidth higher to allow for a longer stability hold-over.
I suppose one might be able to do the math in order to remove all the guess
work, however I have never seen the measured phase noise of the M12+T's 1PPS
or anything similar. So, I am just designing so that the M12+T, the DACs and
my OCXO will be the limiting factors, and not the measured phase resolution.
The reason - because it seems easy enough to do so. Maybe, after all, I
should just go for a faster clock. This would allow for dithering down to
about 2ns-3ns accuracy (same as M12+T). I'll just have to endure the EMI -
keep it away from the sensitive circuitry etc.
What are your thoughts? Am I just being paranoid?
Best regards,
Stephan.
Hi Stephan,
if you need a ps resolution time interval counter for use in a project
of your own, why not simply go out and buy you one? For example here
http://www.acam.de/index.php?id=105
They are not that expensive because they are made to be married with
cheap sensors.
However, you may also follow TVB's suggestion and spend some time on
finding out what resolution you really need. In
http://www.ulrich-bangert.de/html/photo_gallery_44.html
the sigma-tau-diagrams of a uncorrected M12+ pps and that of a sawtooth
corrected pps are drawn in the same diagram. Because the sawtooth
corrected pps values have a different slope the lines meet at app. Tau =
1 day. Build yourself an opinion of your own up to which tau using the
corrected values may make sense!
Regards
Ulrich
-----Ursprüngliche Nachricht-----
Von: time-nuts-bounces@febo.com
[mailto:time-nuts-bounces@febo.com] Im Auftrag von Stephan Sandenbergh
Gesendet: Donnerstag, 29. Juni 2006 15:20
An: time-nuts@febo.com; 'Magnus Danielson'
Betreff: Re: [time-nuts] Linear InterpolatorHi Stephan
Hi,
So you suggest, I take the 10MHz output of my OCXO lock that to a
stable VCXO (say 64MHz as not to be a harmonic multiple of
10MHz) and
then clock my FPGA with the resultant output.
I would rephrase that to say that you should lock your low
jitter VCXO
(of say 64 MHz) to your stable OCXO (of 10 MHz).
Thanks for correcting me. This is actually what I meant.
Oh, what 64 MHz oscillator do you have?
Currently I don't have a 64MHz VCO yet. I'm just weighing my
options. My original idea was too run the FPGA off a 64MHz
free-running XO. This would have given me 15.6ns resolution
with a simple start-stop type phase detector (and not too
much EMI problems). However, in retrospect, I doubt if that
will give me the 1ns dithered accuracy I want. It will be a
shame to add substantial noise to the low 2ns jitter of the
M12+T. I guess the final dithered accuracy depends on one's
pre-averaging time.
Well, I still think it might be better to run off a
free-running XO to have the dithering advantage. My
application requires good stability (ideally sub
ns) between distant locations (maybe in the order of 100s of
meters to 10s of kilometres) on time scales of 100s of
seconds to a few minutes.
I guess one can view the PLL as a very sharp roll-off
low-pass filter. If one could have less jitter (via sawtooth
correction and a good resolution phase detector) at the 1PPS
input in the first place, one could set your PLL bandwidth
higher to allow for a longer stability hold-over.
I suppose one might be able to do the math in order to remove
all the guess work, however I have never seen the measured
phase noise of the M12+T's 1PPS or anything similar. So, I am
just designing so that the M12+T, the DACs and my OCXO will
be the limiting factors, and not the measured phase
resolution. The reason - because it seems easy enough to do
so. Maybe, after all, I should just go for a faster clock.
This would allow for dithering down to about 2ns-3ns accuracy
(same as M12+T). I'll just have to endure the EMI - keep it
away from the sensitive circuitry etc.
What are your thoughts? Am I just being paranoid?
Best regards,
Stephan.
time-nuts mailing list
time-nuts@febo.com
https://www.febo.com/cgi-> bin/mailman/listinfo/time-nuts
if you need a ps resolution time interval counter for use in a project
of your own, why not simply go out and buy you one? For example here
http://www.acam.de/index.php?id=105
They are not that expensive because they are made to be married with
cheap sensors.
Ulrich, Thanks for that link. Very interesting part. And
a google for Time-to-Digital Converter turns up a huge
list of relevant hits.
/tvb
Hi Ulrich,
Thanks for the tip. And, also many thanks to Magnus for introducing me to
the concept of Time-to-Digital conversion. It is a brilliant and yet so
simple technique. (Until yesterday, I blissfully believed that a fast
clocking counter was one's best bet.)
Accordingly, I did a bit of research on the topic:
Google took me to a lot of interesting sites (as Tom van Baak noted).
However, I found only one company, Acam (which is the one you also pointed
out), that sell these things inside an IC.
I also read the article posted earlier by Tom van Baak (Thanks Tom! This is
indeed a very comprehensive article.) It turns out that you can implement a
very elegant linear interpolator using a digital delay line inside a FPGA.
It is called the Vernier technique. From the article I understand that
resolutions of between 10s and 100s of picoseconds have been achieved for
various designs.
Has anyone else used this Vernier technique with delay lines? I seems pretty
neat to me.
It means my hardware doesn't need to change. A software update will do the
trick :)
Regards,
Stephan.
PS: Thanks Ulrich for the link to your M12+T results. I was looking all over
the place for these results for a long time now.
From: "Stephan Sandenbergh" stephan@rrsg.ee.uct.ac.za
Subject: Re: [time-nuts] Linear Interpolator
Date: Fri, 30 Jun 2006 14:02:11 +0200
Message-ID: 002c01c69c3d$053bc8a0$401c9e89@Stephan
Hi Ulrich,
Stephan,
Thanks for the tip. And, also many thanks to Magnus for introducing me to
the concept of Time-to-Digital conversion. It is a brilliant and yet so
simple technique. (Until yesterday, I blissfully believed that a fast
clocking counter was one's best bet.)
Indeed. Once you understood the basic concept, the particular interpolating
technique you choose may vary as you see fit.
I also read the article posted earlier by Tom van Baak (Thanks Tom! This is
indeed a very comprehensive article.) It turns out that you can implement a
very elegant linear interpolator using a digital delay line inside a FPGA.
It is called the Vernier technique. From the article I understand that
resolutions of between 10s and 100s of picoseconds have been achieved for
various designs.
Has anyone else used this Vernier technique with delay lines? I seems pretty
neat to me.
It's what makes the HP5371A/HP5372A tick, it cranks out 200 ps resolution that
way and keep counters at a mear 500 MHz. The HP5370A use a dual oscillator
Vernier trick instead.
It can be a bit of a challenge to get the FPGA to perform reliably thought.
You could do a similar thing with a single delay-line but dual clocks of near
same frequency. That might be a bit more reliable than the dual delay-line
technique.
It means my hardware doesn't need to change. A software update will do the
trick :)
Hehe... ;O)
Cheers,
Magnus
Inspired by Ulrich's lead regarding the high resolution TDC, I asked the
Acam US rep for a quote on the TDC GP2. As Ulrich indicated they are not too
expensive: $28 quantity 1, $26 quantity 10. Sounds great. Temperature
coefficient isn't quoted but it will be considerable - presumably can be
corrected in software.
For me the catch seems to be that they are packaged in a QFN-32. The pin
spacing is 500 microns and the open space between the solder pads is only
200 microns. Perhaps I am too timid but this sounds like trouble for manual
soldering, that's assuming the low cost PCB suppliers could make the
appropriate solder mask. Any comments from the experienced?
Acam makes a dandy evaluation board, the ATMD-GPX, but for this they want
$2298. Oh well.
Brooks
----- Original Message -----
From: "Ulrich Bangert" df6jb@ulrich-bangert.de
To: "'Discussion of precise time and frequency measurement'"
time-nuts@febo.com; "'Magnus Danielson'" cfmd@bredband.net
Sent: Thursday, June 29, 2006 11:41
Subject: Re: [time-nuts] Linear Interpolator
Hi Stephan,
if you need a ps resolution time interval counter for use in a project
of your own, why not simply go out and buy you one? For example here
http://www.acam.de/index.php?id=105
They are not that expensive because they are made to be married with
cheap sensors.
Brooks,
QFN's aren't that bad (you ought to try 0201 SMDs..... Like soldering
dust. QFN's are tight, but with a little technique they solder pretty
easily. I am using a little QFN28 for the CP2102 USB-to-serial converter
on my new FC Oncore Eval Board design. There are a couple of tricks I
have found that work well.
-
When you make your pad pattern in your layout program you want to
make the SMD pads stick out beyond the edges of the package enough to
allow you to get an iron tip in there and create a little solder fillet.
If you use the normal package patterns suggested by the manufacturers it
is almost impossible to manually install the part as there is not enough
pad exposed. I have done this with almost every component layout I use
when designing boards. The pads are always a little bit bigger so that I
can manually build or rework if needed. This step is really important. -
First glue the QFN to the board with a little TINY dab of slow curing
epoxy. You want to use the slow stuff because it gives you enough time
to push the IC around with a couple of toothpicks until it is aligned. -
Liberally flux the part to make sure you get good wetting.
-
With a small tip (I usually just use my good old Weller) and small
diameter solder (.015" if you can get it), carefully form bridges
between the pads on the board and the pads on the QFN. DO NOT drag the
iron. You want it to glide on a thin layer of solder. If you drag the
tip you risk pulling the pads off the board and/or the QFN itself. Don't
worry about bridges at this point. Add more flux if you need to. The
idea is to keep the surface tension high so that the solder wants to
form bumps rather than smearing. -
Once you are happy that you have made connections to all pads, work
back around the part with the tiny (.015" I think) solder wick and the
iron. Again, you only want to slide around without dragging. The solder
wick will pull up any excess solder but leave a perfect little bond
underneath the QFN and a nice fillet on the side. Again, be liberal with
the flux. If the solder gets too dry and/or overheated it will tend to
smear between pads instead of balling up and separating.
See mom, my 2 week DoD soldering class really did come in handy! ;-)
Randy
P.S. I hope I never have to do this with lead-free solder.
-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Brooks Shera
Sent: Friday, June 30, 2006 2:54 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Linear Interpolator
Inspired by Ulrich's lead regarding the high resolution TDC, I asked the
Acam US rep for a quote on the TDC GP2. As Ulrich indicated they are not
too
expensive: $28 quantity 1, $26 quantity 10. Sounds great. Temperature
coefficient isn't quoted but it will be considerable - presumably can be
corrected in software.
For me the catch seems to be that they are packaged in a QFN-32. The
pin
spacing is 500 microns and the open space between the solder pads is
only 200 microns. Perhaps I am too timid but this sounds like trouble
for manual soldering, that's assuming the low cost PCB suppliers could
make the appropriate solder mask. Any comments from the experienced?
Acam makes a dandy evaluation board, the ATMD-GPX, but for this they
want
$2298. Oh well.
Brooks
Hi Brooks:
I too got the quote on the GP2 and checked the ExpressPCB software
package that does both schematic capture and board layout and it has a
template for the QFN32 package. For comparison I placed the ICS525
template right beside the QFN32. The ICS525 has 1/4 pitch (0.025") but
the QFN is 0.5 mm (0.02") which is a little finer.
I have been able to mount the ICS525 using either solder paste or just
an iron. For more on working with SMT parts see my web page:
http://www.pacificsites.com/~brooke/SMT.shtml
I agree with Randy's comment that the pad on the board needs to be
longer to give an iron a place to work. Also solder mask sure is a big
help, and that's why it exists.
If there's a desired circuit I'm fairly sure I could build it.
Have Fun,
Brooke Clarke
--
w/Java http://www.PRC68.com
w/o Java http://www.pacificsites.com/~brooke/PRC68COM.shtml
http://www.precisionclock.com
Brooks Shera wrote:
Inspired by Ulrich's lead regarding the high resolution TDC, I asked the
Acam US rep for a quote on the TDC GP2. As Ulrich indicated they are not too
expensive: $28 quantity 1, $26 quantity 10. Sounds great. Temperature
coefficient isn't quoted but it will be considerable - presumably can be
corrected in software.
For me the catch seems to be that they are packaged in a QFN-32. The pin
spacing is 500 microns and the open space between the solder pads is only
200 microns. Perhaps I am too timid but this sounds like trouble for manual
soldering, that's assuming the low cost PCB suppliers could make the
appropriate solder mask. Any comments from the experienced?
Acam makes a dandy evaluation board, the ATMD-GPX, but for this they want
$2298. Oh well.
Brooks
----- Original Message -----
From: "Ulrich Bangert" df6jb@ulrich-bangert.de
To: "'Discussion of precise time and frequency measurement'"
time-nuts@febo.com; "'Magnus Danielson'" cfmd@bredband.net
Sent: Thursday, June 29, 2006 11:41
Subject: Re: [time-nuts] Linear Interpolator
Hi Stephan,
if you need a ps resolution time interval counter for use in a project
of your own, why not simply go out and buy you one? For example here
http://www.acam.de/index.php?id=105
They are not that expensive because they are made to be married with
cheap sensors.
time-nuts mailing list
time-nuts@febo.com
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Hi Stephan,
a lot of excellent scientifical reading is availabale on the net about
that topic. My personal #1 reference is "A Jitter Characterization Sytem
Using a Component-Invariant Vernier Delay Line" by Antonio H. Chan.
There are other companies to sell ready to go ps resolution stuff but
not at the prices of ACAM.
Regards
Ulrich
-----Ursprüngliche Nachricht-----
Von: time-nuts-bounces@febo.com
[mailto:time-nuts-bounces@febo.com] Im Auftrag von Stephan Sandenbergh
Gesendet: Freitag, 30. Juni 2006 14:02
An: 'Discussion of precise time and frequency measurement'
Betreff: Re: [time-nuts] Linear Interpolator
Hi Ulrich,
Thanks for the tip. And, also many thanks to Magnus for
introducing me to the concept of Time-to-Digital conversion.
It is a brilliant and yet so simple technique. (Until
yesterday, I blissfully believed that a fast clocking counter
was one's best bet.)
Accordingly, I did a bit of research on the topic:
Google took me to a lot of interesting sites (as Tom van Baak
noted). However, I found only one company, Acam (which is the
one you also pointed out), that sell these things inside an IC.
I also read the article posted earlier by Tom van Baak
(Thanks Tom! This is indeed a very comprehensive article.) It
turns out that you can implement a very elegant linear
interpolator using a digital delay line inside a FPGA. It is
called the Vernier technique. From the article I understand
that resolutions of between 10s and 100s of picoseconds have
been achieved for various designs.
Has anyone else used this Vernier technique with delay lines?
I seems pretty neat to me.
It means my hardware doesn't need to change. A software
update will do the
trick :)
Regards,
Stephan.
PS: Thanks Ulrich for the link to your M12+T results. I was
looking all over the place for these results for a long time now.
time-nuts mailing list
time-nuts@febo.com
https://www.febo.com/cgi-> bin/mailman/listinfo/time-nuts
Hi Ulrich,
Thanks for the useful link.
Regards,
Stephan.
-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Ulrich Bangert
Sent: 01 July 2006 05:39 PM
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] Linear Interpolator
Hi Stephan,
a lot of excellent scientifical reading is availabale on the net about
that topic. My personal #1 reference is "A Jitter Characterization Sytem
Using a Component-Invariant Vernier Delay Line" by Antonio H. Chan.
There are other companies to sell ready to go ps resolution stuff but
not at the prices of ACAM.
Regards
Ulrich
-----Ursprüngliche Nachricht-----
Von: time-nuts-bounces@febo.com
[mailto:time-nuts-bounces@febo.com] Im Auftrag von Stephan Sandenbergh
Gesendet: Freitag, 30. Juni 2006 14:02
An: 'Discussion of precise time and frequency measurement'
Betreff: Re: [time-nuts] Linear Interpolator
Hi Ulrich,
Thanks for the tip. And, also many thanks to Magnus for
introducing me to the concept of Time-to-Digital conversion.
It is a brilliant and yet so simple technique. (Until
yesterday, I blissfully believed that a fast clocking counter
was one's best bet.)
Accordingly, I did a bit of research on the topic:
Google took me to a lot of interesting sites (as Tom van Baak
noted). However, I found only one company, Acam (which is the
one you also pointed out), that sell these things inside an IC.
I also read the article posted earlier by Tom van Baak
(Thanks Tom! This is indeed a very comprehensive article.) It
turns out that you can implement a very elegant linear
interpolator using a digital delay line inside a FPGA. It is
called the Vernier technique. From the article I understand
that resolutions of between 10s and 100s of picoseconds have
been achieved for various designs.
Has anyone else used this Vernier technique with delay lines?
I seems pretty neat to me.
It means my hardware doesn't need to change. A software
update will do the
trick :)
Regards,
Stephan.
PS: Thanks Ulrich for the link to your M12+T results. I was
looking all over the place for these results for a long time now.
time-nuts mailing list
time-nuts@febo.com
https://www.febo.com/cgi-> bin/mailman/listinfo/time-nuts
time-nuts mailing list
time-nuts@febo.com
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
Hi fellow time-nuts,
Stephan Sandenbergh wrote:
I also read the article posted earlier by Tom van Baak (Thanks Tom! This is
indeed a very comprehensive article.) It turns out that you can implement a
very elegant linear interpolator using a digital delay line inside a FPGA.
It is called the Vernier technique. From the article I understand that
resolutions of between 10s and 100s of picoseconds have been achieved for
various designs.
Has anyone else used this Vernier technique with delay lines? I seems
pretty
neat to me.
I'll take this opportunity to plug something I wrote for last year's
UKW-Tagung (VHF-conference) in Weinheim:
"Increasing the resolution of reciprocal counters" which shows how to
use the Digital Clock Management feature of the Spartan series of FPGA
to achieve a 16-fold increase in resolution, resulting in a 625ps
resolution (1.6GHz reference) at the moment.
This technique indeed uses a similar kind of delay-line, but integrated
in the DCM which provides calibration and phase-shifting.
http://a48046.upc-a.chello.nl/~paul/Reciproke.pdf
Regards, Paul Boven.
Excellent paper, nice to see some amateurs working at home-brew still!
john
At 06:54 PM 7/20/2006, you wrote:
Hi fellow time-nuts,
Stephan Sandenbergh wrote:
I also read the article posted earlier by Tom van Baak (Thanks Tom! This is
indeed a very comprehensive article.) It turns out that you can implement a
very elegant linear interpolator using a digital delay line inside a FPGA.
It is called the Vernier technique. From the article I understand that
resolutions of between 10s and 100s of picoseconds have been achieved for
various designs.
Has anyone else used this Vernier technique with delay lines? I seems
pretty
neat to me.
I'll take this opportunity to plug something I wrote for last year's
UKW-Tagung (VHF-conference) in Weinheim:
"Increasing the resolution of reciprocal counters" which shows how to
use the Digital Clock Management feature of the Spartan series of FPGA
to achieve a 16-fold increase in resolution, resulting in a 625ps
resolution (1.6GHz reference) at the moment.
This technique indeed uses a similar kind of delay-line, but integrated
in the DCM which provides calibration and phase-shifting.
http://a48046.upc-a.chello.nl/~paul/Reciproke.pdf
Regards, Paul Boven.
time-nuts mailing list
time-nuts@febo.com
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
From: Paul Boven p.boven@chello.nl
Subject: Re: [time-nuts] Linear Interpolator
Date: Fri, 21 Jul 2006 00:54:35 +0200
Message-ID: 44C009AB.7070609@chello.nl
Hi fellow time-nuts,
Stephan Sandenbergh wrote:
I also read the article posted earlier by Tom van Baak (Thanks Tom! This is
indeed a very comprehensive article.) It turns out that you can implement a
very elegant linear interpolator using a digital delay line inside a FPGA.
It is called the Vernier technique. From the article I understand that
resolutions of between 10s and 100s of picoseconds have been achieved for
various designs.
Has anyone else used this Vernier technique with delay lines? I seems
pretty
neat to me.
I'll take this opportunity to plug something I wrote for last year's
UKW-Tagung (VHF-conference) in Weinheim:
"Increasing the resolution of reciprocal counters" which shows how to
use the Digital Clock Management feature of the Spartan series of FPGA
to achieve a 16-fold increase in resolution, resulting in a 625ps
resolution (1.6GHz reference) at the moment.
This technique indeed uses a similar kind of delay-line, but integrated
in the DCM which provides calibration and phase-shifting.
Interesting. The Virtex-4 and Virtex-5 families have programable input delays,
in the Virtex-4 case with about 78 ps resolution. I'm sure someone will come up
with a method to use that.
Cheers,
Magnus