Hi All, Is it possible to generate RFNoC blocks for the B210? I can't find a lot of information about it. Can some one show me the URL if there is a website talking about it? Cheers

There is no conceptual reason why you can’t build an RFNoC design on B210, it uses the same USRP3 base architecture and FPGA source files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all the implementation work for RFNoC is done using Xilinx’s Vivado design tools which support only the newer FPGA architectures like Zynq (Artix) and Kintex…Spartan6 users are stuck with ISE14 forever, so in practical terms, no, it’s not possible without you completely recreating all that infrastructure. -Ian > On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users <usrp-users@lists.ettus.com> wrote: > > Hi All, > Is it possible to generate RFNoC blocks for the B210? I can't find a lot of information about it. Can some one show me the URL if there is a website talking about it? > > Cheers > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Thank you On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> wrote: > There is no conceptual reason why you can’t build an RFNoC design on B210, > it uses the same USRP3 base architecture and FPGA source files….*HOWEVER*…. > B210 is implemented with a Spartan6 FPGA and all the implementation work > for RFNoC is done using Xilinx’s Vivado design tools which support only the > newer FPGA architectures like Zynq (Artix) and Kintex…Spartan6 users are > stuck with ISE14 forever, so in practical terms, no, it’s not possible > without you completely recreating all that infrastructure. > > -Ian > > > On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users < > usrp-users@lists.ettus.com> wrote: > > > > Hi All, > > Is it possible to generate RFNoC blocks for the B210? I can't find a lot > of information about it. Can some one show me the URL if there is a > website talking about it? > > > > Cheers > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

To give an uplifting spin to all this: Now, also, although larger than the one on the B200, the B210's FPGA isn't really large unoccupied, so the amount of logic that you could even hypothetically put in there is limited. Why's that uplifiting? That FPGA was chosen for the board because there's usually little need to do anything but the hardware interfacing and the DDC/DUC in the FPGA. The B210 can, with good USB3 controllers, pretty much directly hand through its analog bandwidth to a computer. So, unless you have a workload that your PC including GPU and whatnot can't achieve, you don't even have to think about implementing things on the B210's FPGA – and frankly, I've got no idea what'd be easy to do on the free space of a B210 but impossible on a high-end PC. And a high-end PC is still cheaper than a ISE14 license. Only thing that comes into mind is the latency restrictions you incur with USB; that's really something that no amount of computing power on the host computer side could solve. So, maybe, if I can encourage you to discuss your specific application, we can find a sensible solution on what to put on the SDR peripheral device itself, and what to do on your PC? Best regards, Marcus On Thu, 2018-06-28 at 15:56 -0700, Peter Sanchez via USRP-users wrote: > Thank you > > On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> > wrote: > > There is no conceptual reason why you can’t build an RFNoC design > > on B210, it uses the same USRP3 base architecture and FPGA source > > files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all > > the implementation work for RFNoC is done using Xilinx’s Vivado > > design tools which support only the newer FPGA architectures like > > Zynq (Artix) and Kintex…Spartan6 users are stuck with ISE14 > > forever, so in practical terms, no, it’s not possible without you > > completely recreating all that infrastructure. > > > > -Ian > > > > > On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users <usrp-u > > sers@lists.ettus.com> wrote: > > > > > > Hi All, > > > Is it possible to generate RFNoC blocks for the B210? I can't > > find a lot of information about it. Can some one show me the URL if > > there is a website talking about it? > > > > > > Cheers > > > _______________________________________________ > > > USRP-users mailing list > > > USRP-users@lists.ettus.com > > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.co > > m > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

I second RFNoC for the B series would be great. They're an incredibly popular and affordable series and I feel a little left out of the capabilities of RFNoC due to the Spartan6. Bringing the Artix to the B-series or supporting the Spartan6 could both be options I'd love to see. (Just a community vote :) ) On Thu, Jun 28, 2018 at 6:56 PM, Peter Sanchez via USRP-users < usrp-users@lists.ettus.com> wrote: > Thank you > > On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> wrote: > >> There is no conceptual reason why you can’t build an RFNoC design on >> B210, it uses the same USRP3 base architecture and FPGA source >> files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all the >> implementation work for RFNoC is done using Xilinx’s Vivado design tools >> which support only the newer FPGA architectures like Zynq (Artix) and >> Kintex…Spartan6 users are stuck with ISE14 forever, so in practical terms, >> no, it’s not possible without you completely recreating all that >> infrastructure. >> >> -Ian >> >> > On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> > >> > Hi All, >> > Is it possible to generate RFNoC blocks for the B210? I can't find a >> lot of information about it. Can some one show me the URL if there is a >> website talking about it? >> > >> > Cheers >> > _______________________________________________ >> > USRP-users mailing list >> > USRP-users@lists.ettus.com >> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

I think what would be more useful is a low-end USRP (low price like B200) that is RFNOC-capable. I guess that might be something like an E310 in a white case? On Fri, Jun 29, 2018 at 9:12 AM GhostOp14 via USRP-users < usrp-users@lists.ettus.com> wrote: > I second RFNoC for the B series would be great. They're an incredibly > popular and affordable series and I feel a little left out of the > capabilities of RFNoC due to the Spartan6. Bringing the Artix to the > B-series or supporting the Spartan6 could both be options I'd love to see. > (Just a community vote :) ) > > On Thu, Jun 28, 2018 at 6:56 PM, Peter Sanchez via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Thank you >> >> On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> >> wrote: >> >>> There is no conceptual reason why you can’t build an RFNoC design on >>> B210, it uses the same USRP3 base architecture and FPGA source >>> files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all the >>> implementation work for RFNoC is done using Xilinx’s Vivado design tools >>> which support only the newer FPGA architectures like Zynq (Artix) and >>> Kintex…Spartan6 users are stuck with ISE14 forever, so in practical terms, >>> no, it’s not possible without you completely recreating all that >>> infrastructure. >>> >>> -Ian >>> >>> > On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users < >>> usrp-users@lists.ettus.com> wrote: >>> > >>> > Hi All, >>> > Is it possible to generate RFNoC blocks for the B210? I can't find a >>> lot of information about it. Can some one show me the URL if there is a >>> website talking about it? >>> > >>> > Cheers >>> > _______________________________________________ >>> > USRP-users mailing list >>> > USRP-users@lists.ettus.com >>> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > -- Very Respectfully, Dan CaJacob

Errrrr no. B200 has approximately the same number of FPGA logic gates as E310, B210 twice that amount. The current design is simply larger than it needs to be because it shares all it’s code with X300, I could have made it much smaller had there been a good reason to. The FPGA was simply chosen because it was the biggest and newest available when that project was begun. The Vivado/ISE split wasn’t customer visible at that point in time, remember X300 was also ISE based at initial release. It remains a potent platform for capable FPGA designers to do custom stuff on, just not RFNoC. -Ian > On Jun 29, 2018, at 1:35 AM, Marcus Müller <marcus.mueller@ettus.com> wrote: > > To give an uplifting spin to all this: > > Now, also, although larger than the one on the B200, the B210's FPGA > isn't really large unoccupied, so the amount of logic that you could > even hypothetically put in there is limited. Why's that uplifiting? > > That FPGA was chosen for the board because there's usually little need > to do anything but the hardware interfacing and the DDC/DUC in the > FPGA. The B210 can, with good USB3 controllers, pretty much directly > hand through its analog bandwidth to a computer. So, unless you have a > workload that your PC including GPU and whatnot can't achieve, you > don't even have to think about implementing things on the B210's FPGA – > and frankly, I've got no idea what'd be easy to do on the free space of > a B210 but impossible on a high-end PC. And a high-end PC is still > cheaper than a ISE14 license. > > Only thing that comes into mind is the latency restrictions you incur > with USB; that's really something that no amount of computing power on > the host computer side could solve. > > So, maybe, if I can encourage you to discuss your specific application, > we can find a sensible solution on what to put on the SDR peripheral > device itself, and what to do on your PC? > > Best regards, > Marcus > > On Thu, 2018-06-28 at 15:56 -0700, Peter Sanchez via USRP-users wrote: >> Thank you >> >> On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> >> wrote: >>> There is no conceptual reason why you can’t build an RFNoC design >>> on B210, it uses the same USRP3 base architecture and FPGA source >>> files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all >>> the implementation work for RFNoC is done using Xilinx’s Vivado >>> design tools which support only the newer FPGA architectures like >>> Zynq (Artix) and Kintex…Spartan6 users are stuck with ISE14 >>> forever, so in practical terms, no, it’s not possible without you >>> completely recreating all that infrastructure. >>> >>> -Ian >>> >>>> On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users <usrp-u >>> sers@lists.ettus.com> wrote: >>>> >>>> Hi All, >>>> Is it possible to generate RFNoC blocks for the B210? I can't >>> find a lot of information about it. Can some one show me the URL if >>> there is a website talking about it? >>>> >>>> Cheers >>>> _______________________________________________ >>>> USRP-users mailing list >>>> USRP-users@lists.ettus.com >>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.co >>> m >>> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

What I meant and didn't explain well enough is a potential new Ettus product would be a Zynq-based B2X0 clone. That would be RFNOC-capable. On Fri, Jun 29, 2018 at 2:32 PM Ian Buckley via USRP-users < usrp-users@lists.ettus.com> wrote: > Errrrr no. > > B200 has approximately the same number of FPGA logic gates as E310, B210 > twice that amount. > The current design is simply larger than it needs to be because it shares > all it’s code with X300, I could have made it much smaller had there been a > good reason to. > > The FPGA was simply chosen because it was the biggest and newest available > when that project was begun. > The Vivado/ISE split wasn’t customer visible at that point in time, > remember X300 was also ISE based at initial release. > > It remains a potent platform for capable FPGA designers to do custom stuff > on, just not RFNoC. > -Ian > > > > On Jun 29, 2018, at 1:35 AM, Marcus Müller <marcus.mueller@ettus.com> > wrote: > > > > To give an uplifting spin to all this: > > > > Now, also, although larger than the one on the B200, the B210's FPGA > > isn't really large unoccupied, so the amount of logic that you could > > even hypothetically put in there is limited. Why's that uplifiting? > > > > That FPGA was chosen for the board because there's usually little need > > to do anything but the hardware interfacing and the DDC/DUC in the > > FPGA. The B210 can, with good USB3 controllers, pretty much directly > > hand through its analog bandwidth to a computer. So, unless you have a > > workload that your PC including GPU and whatnot can't achieve, you > > don't even have to think about implementing things on the B210's FPGA – > > and frankly, I've got no idea what'd be easy to do on the free space of > > a B210 but impossible on a high-end PC. And a high-end PC is still > > cheaper than a ISE14 license. > > > > Only thing that comes into mind is the latency restrictions you incur > > with USB; that's really something that no amount of computing power on > > the host computer side could solve. > > > > So, maybe, if I can encourage you to discuss your specific application, > > we can find a sensible solution on what to put on the SDR peripheral > > device itself, and what to do on your PC? > > > > Best regards, > > Marcus > > > > On Thu, 2018-06-28 at 15:56 -0700, Peter Sanchez via USRP-users wrote: > >> Thank you > >> > >> On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> > >> wrote: > >>> There is no conceptual reason why you can’t build an RFNoC design > >>> on B210, it uses the same USRP3 base architecture and FPGA source > >>> files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all > >>> the implementation work for RFNoC is done using Xilinx’s Vivado > >>> design tools which support only the newer FPGA architectures like > >>> Zynq (Artix) and Kintex…Spartan6 users are stuck with ISE14 > >>> forever, so in practical terms, no, it’s not possible without you > >>> completely recreating all that infrastructure. > >>> > >>> -Ian > >>> > >>>> On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users <usrp-u > >>> sers@lists.ettus.com> wrote: > >>>> > >>>> Hi All, > >>>> Is it possible to generate RFNoC blocks for the B210? I can't > >>> find a lot of information about it. Can some one show me the URL if > >>> there is a website talking about it? > >>>> > >>>> Cheers > >>>> _______________________________________________ > >>>> USRP-users mailing list > >>>> USRP-users@lists.ettus.com > >>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.co > >>> m > >>> > >> > >> _______________________________________________ > >> USRP-users mailing list > >> USRP-users@lists.ettus.com > >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > -- Very Respectfully, Dan CaJacob

Hi Dan. Such a product is in the works. It was mentioned in Manuel Uhm's presentation at GRCon 2017-- the USRP E320. Single board approximately the size of a B210, AD9361, RFNoC-capable with larger Zynq FPGA than E310 (XC7Z045). Ettus Research intends to demo the E320 at GRCon 2018, so sign up today (early bird registration ends tomorrow)! https://www.eventbrite.com/e/gnu-radio-conference-2018-tickets-42793672025 -Robin On Fri, Jun 29, 2018 at 11:40 AM, Dan CaJacob via USRP-users < usrp-users@lists.ettus.com> wrote: > What I meant and didn't explain well enough is a potential new Ettus > product would be a Zynq-based B2X0 clone. That would be RFNOC-capable. > > On Fri, Jun 29, 2018 at 2:32 PM Ian Buckley via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Errrrr no. >> >> B200 has approximately the same number of FPGA logic gates as E310, B210 >> twice that amount. >> The current design is simply larger than it needs to be because it shares >> all it’s code with X300, I could have made it much smaller had there been a >> good reason to. >> >> The FPGA was simply chosen because it was the biggest and newest >> available when that project was begun. >> The Vivado/ISE split wasn’t customer visible at that point in time, >> remember X300 was also ISE based at initial release. >> >> It remains a potent platform for capable FPGA designers to do custom >> stuff on, just not RFNoC. >> -Ian >> >> >> > On Jun 29, 2018, at 1:35 AM, Marcus Müller <marcus.mueller@ettus.com> >> wrote: >> > >> > To give an uplifting spin to all this: >> > >> > Now, also, although larger than the one on the B200, the B210's FPGA >> > isn't really large unoccupied, so the amount of logic that you could >> > even hypothetically put in there is limited. Why's that uplifiting? >> > >> > That FPGA was chosen for the board because there's usually little need >> > to do anything but the hardware interfacing and the DDC/DUC in the >> > FPGA. The B210 can, with good USB3 controllers, pretty much directly >> > hand through its analog bandwidth to a computer. So, unless you have a >> > workload that your PC including GPU and whatnot can't achieve, you >> > don't even have to think about implementing things on the B210's FPGA – >> > and frankly, I've got no idea what'd be easy to do on the free space of >> > a B210 but impossible on a high-end PC. And a high-end PC is still >> > cheaper than a ISE14 license. >> > >> > Only thing that comes into mind is the latency restrictions you incur >> > with USB; that's really something that no amount of computing power on >> > the host computer side could solve. >> > >> > So, maybe, if I can encourage you to discuss your specific application, >> > we can find a sensible solution on what to put on the SDR peripheral >> > device itself, and what to do on your PC? >> > >> > Best regards, >> > Marcus >> > >> > On Thu, 2018-06-28 at 15:56 -0700, Peter Sanchez via USRP-users wrote: >> >> Thank you >> >> >> >> On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> >> >> wrote: >> >>> There is no conceptual reason why you can’t build an RFNoC design >> >>> on B210, it uses the same USRP3 base architecture and FPGA source >> >>> files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all >> >>> the implementation work for RFNoC is done using Xilinx’s Vivado >> >>> design tools which support only the newer FPGA architectures like >> >>> Zynq (Artix) and Kintex…Spartan6 users are stuck with ISE14 >> >>> forever, so in practical terms, no, it’s not possible without you >> >>> completely recreating all that infrastructure. >> >>> >> >>> -Ian >> >>> >> >>>> On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users <usrp-u >> >>> sers@lists.ettus.com> wrote: >> >>>> >> >>>> Hi All, >> >>>> Is it possible to generate RFNoC blocks for the B210? I can't >> >>> find a lot of information about it. Can some one show me the URL if >> >>> there is a website talking about it? >> >>>> >> >>>> Cheers >> >>>> _______________________________________________ >> >>>> USRP-users mailing list >> >>>> USRP-users@lists.ettus.com >> >>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.co >> >>> m >> >>> >> >> >> >> _______________________________________________ >> >> USRP-users mailing list >> >> USRP-users@lists.ettus.com >> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > -- > Very Respectfully, > > Dan CaJacob > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Appreciate the feedback. Marcus, we have a project using RFNoC blocks on the X310 to run this workflow, 2x Rx --> Splitstream for each RX --> DDC for each split stream out --> FFT Sink. We would like to do the same on the B210. This was overwhelming our CPU + GPU before we switched to RFNoC on the X310. We can deal with some latency as long as it is within reason. If you think there is a way to do this workload on the PC without reducing bandwidth I can give it a try. Thanks On Fri, Jun 29, 2018 at 1:35 AM, Marcus Müller <marcus.mueller@ettus.com> wrote: > To give an uplifting spin to all this: > > Now, also, although larger than the one on the B200, the B210's FPGA > isn't really large unoccupied, so the amount of logic that you could > even hypothetically put in there is limited. Why's that uplifiting? > > That FPGA was chosen for the board because there's usually little need > to do anything but the hardware interfacing and the DDC/DUC in the > FPGA. The B210 can, with good USB3 controllers, pretty much directly > hand through its analog bandwidth to a computer. So, unless you have a > workload that your PC including GPU and whatnot can't achieve, you > don't even have to think about implementing things on the B210's FPGA – > and frankly, I've got no idea what'd be easy to do on the free space of > a B210 but impossible on a high-end PC. And a high-end PC is still > cheaper than a ISE14 license. > > Only thing that comes into mind is the latency restrictions you incur > with USB; that's really something that no amount of computing power on > the host computer side could solve. > > So, maybe, if I can encourage you to discuss your specific application, > we can find a sensible solution on what to put on the SDR peripheral > device itself, and what to do on your PC? > > Best regards, > Marcus > > On Thu, 2018-06-28 at 15:56 -0700, Peter Sanchez via USRP-users wrote: > > Thank you > > > > On Thu, Jun 28, 2018 at 2:01 PM, Ian Buckley <ianb@ionconcepts.com> > > wrote: > > > There is no conceptual reason why you can’t build an RFNoC design > > > on B210, it uses the same USRP3 base architecture and FPGA source > > > files….*HOWEVER*…. B210 is implemented with a Spartan6 FPGA and all > > > the implementation work for RFNoC is done using Xilinx’s Vivado > > > design tools which support only the newer FPGA architectures like > > > Zynq (Artix) and Kintex…Spartan6 users are stuck with ISE14 > > > forever, so in practical terms, no, it’s not possible without you > > > completely recreating all that infrastructure. > > > > > > -Ian > > > > > > > On Jun 28, 2018, at 1:47 PM, Peter Sanchez via USRP-users <usrp-u > > > sers@lists.ettus.com> wrote: > > > > > > > > Hi All, > > > > Is it possible to generate RFNoC blocks for the B210? I can't > > > find a lot of information about it. Can some one show me the URL if > > > there is a website talking about it? > > > > > > > > Cheers > > > > _______________________________________________ > > > > USRP-users mailing list > > > > USRP-users@lists.ettus.com > > > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.co > > > m > > > > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >