On Wed, Apr 25, 2012 at 5:50 AM, Bill Dailey docdailey@gmail.com wrote:

It might be time for a group project to design a "Pictic III" that uses
parts that are readily available.  Today I'd build it around an Arduino
rather than a PIC even if the cost is more.  Arduino is programmable by
anyone and plugs into a USB port, no onwwouldhave to supply programed
chips and because it is so easy to program maybe some users would try to
make improvements and offer them to others.

Other suggestions to do something like this have come up on this list but
then someone starts talking about using some specialized technology that
99.99% of the readers don't know (like FPGAs)  I'd like to see it done with
25 cent parts and technology a beginner can master

Chris Albertson
Redondo Beach, California

Chris: I concur. Arduino base would allow simple extension to 'net
control as well.
Don

Chris Albertson

--
"Neither the voice of authority nor the weight of reason and argument
are as significant as experiment, for thence comes quiet to the mind."
R. Bacon
"If you don't know what it is, don't poke it."
Ghost in the Shell

Dr. Don Latham AJ7LL
Six Mile Systems LLP
17850 Six Mile Road
POB 134
Huson, MT, 59846
VOX 406-626-4304
www.lightningforensics.com
www.sixmilesystems.com

I forgot to add that a simple redrafting of the II as an Arduino shield
with appropriate chips and chip passives would accomplish the desired
end without losing the very careful engineering and testing that has
already been done?
Would be nice to have a way to change caps without soldering as well,
maybe just some .1" jumpers?
Don

--
"Neither the voice of authority nor the weight of reason and argument
are as significant as experiment, for thence comes quiet to the mind."
R. Bacon
"If you don't know what it is, don't poke it."
Ghost in the Shell

Dr. Don Latham AJ7LL
Six Mile Systems LLP
17850 Six Mile Road
POB 134
Huson, MT, 59846
VOX 406-626-4304
www.lightningforensics.com
www.sixmilesystems.com

I still have a supply of boards and most parts including the 74ac175 but no
interest in assembly or the kitting process. If someone would like to take
this on then I could provide the boards etc ... in bulk. Because of my
limited space the kitting process takes several hours to do them one at time
:-(

Stanley

----- Original Message -----
From: "Don Latham" djl@montana.com
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com
Sent: Wednesday, April 25, 2012 11:37 AM
Subject: Re: [time-nuts] PICTIC II ready-made?

On Wed, Apr 25, 2012 at 9:37 AM, Don Latham djl@montana.com wrote:

Yes, MOST of the design could be re-used.  As an Arduino shield there is no
need for a PIC or RS-232 interface becusethe Arduino does that function.
You'd need to replace the 74ACT175 part but that is not hard.

About changing the cap values without soldering.  I guess you could push
the leads into a 0.1 inch header strip or install several and use a DIP
switch to select which are "in".  But I don't know if the extra inductance
al that wiring adds is enough to worry about.

--

Chris Albertson
Redondo Beach, California

On Wed, 25 Apr 2012 08:45:52 -0700
Chris Albertson albertson.chris@gmail.com wrote:

May i ask what makes the arduino programable by "anyone" ?
Sofar, i only had a look at the hardware of arduino, but never looked
at the software side, as for me, who is regularly writing C code for
bare metal uC applications, the software part is solved if i know that
gcc can generate code for the architecture in question.

The thing is, we want to get into a region of mesurment precision,
that requires good and high quality devices and/or heavy post processing.
Most of the devices needed are pretty advanced. A PICTIC II like Nutt
Interpolator can be build using a higher frequency XO with lower jitter
and using higher quality components (eg ECL devices instead of 74HC, or
better ADCs) which could lead to a magnitude or two of precision enhancement.
But these devices are not as easy to handle as the ones used in the PICTIC II.
They would be all SMD with smaller pitch than 1.27mm (mostly 0.63mm,
some 0.5mm), nothing you'd solder by hand if you have not at least some
experience and an either a good sight or a microscope or similar.

On the other hand, i am pretty sure that a 100 pieces production run
could be done with all the interest on this mailinglist. And with that
you'd get probably below 100USD for a PICTIC II like system. Even if
using more expensive components.

		Attila Kinali

--
Why does it take years to find the answers to
the questions one should have asked long ago?

Chris Albertson wrote:

The time to digital converter (TDC) section is merely an interpolator
that measures the delay of a synchroniser.
The TDC range should be about 2 clock periods to accommodate the range
of synchroniser delays and to facilitate calibration.
Unless one is changing the synchroniser clock period there is no need to
vary the TDC gain.
The SR620 uses a similar interpolator and has only a single interpolator
range.
The range is extended by counting the number of synchroniser clock
periods between synchroniser output transitions of interest.
When measuring the time interval between 2 signals a pair of
synchronisers and interpolators are used.

Interpolator nonlinearity can be measured by using a statistical fill
the buckets technique which uses nothing but a pair of noisy
asynchronous oscillators with high reverse isolation to avoid injection
locking.

If a suitable ADC is used the interpolator can be simplified
considerably whilst improving its performance.
Minor nonlinearities are of little significance, as long as they are
repeatable and relatively stable they can be easily corrected in software.

Bruce

Hi Bruce,

On Thu, 26 Apr 2012 07:15:41 +1200
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Could you tell a little bit more about what a "suitable ADC" for
a time interpolator is? And how exactly does it help to simplify
the interpolator?

		Attila Kinali

--
Why does it take years to find the answers to
the questions one should have asked long ago?

If you guys go the PIC route, I'm always happy to burn them for the
group for cheap.  I think in the past I was doing 5 bucks for the
first one (including delivery) plus $2.50 for each additional.  I
still have a ton of those plastic chip tubes for mailing them so the
pins don't get bent.

-Bob

On Wed, Apr 25, 2012 at 11:44 AM, Stanley timenuts@n4iqt.com wrote:

Attila Kinali wrote:

If a capacitive input charge redistribution ADC is used the interpolator
output capacitor can be directly connected to it.
This eliminates the output buffer amp with its unknown settling time as
well as the associated gain and offset adjustements.
The TDC capacitor merely acts as temporary charge storage to ensure the
ADC input voltage limits arent exceeded during the charging phase.
The charge is redistributed between the external capacitor and the ADC
sampling capacitance with a time constant set the ADC sampling switch on
resistance.
All the calibration adjustments can be eliminated and replaced by
software calibration if reasonably close tolerance parts are used.

Most of the ADCs built into current microprocessors are capacitive input
charge redistribution ADCs.
One just needs to ensure that the ADC input leakage current is
sufficiently small.
The specified pin leakage current test limits are considerably higher
than the actual leakage.
If an external ADC is used higher resolution is possible.

The addition of a ground plane to the PCB should also improve the
perfformance.
The current source also needs a little tweaking (high frequency
decoupling of the transistor emitter and base from the opamp) to improve
its transient response.

Bruce

On Thu, 26 Apr 2012 08:00:17 +1200
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Quite interesting... Thanks a lot!

		Attila Kinali

--
Why does it take years to find the answers to
the questions one should have asked long ago?

About replacing the 74ACT175... there´s a company called "Potato Semi"
(well.. they make "chips", right?) whose sole business is to make damn
fast 74 logic. Their chips can be bought at ebay in small quantities.
Look at this 600MHz D flip flop:

http://www.potatosemi.com/potatosemiweb/datasheet/PO74G74A.pdf

Daniel

Em 25/04/2012 16:15, Bruce Griffiths escreveu:

On Wed, Apr 25, 2012 at 12:11 PM, Attila Kinali attila@kinali.ch wrote:

I can do the same thing too.  But there is a steep learning curve for most
people.  What makes the Arduino easy for beginners is the combination of...

1. A boot loader that makes the Adruino self programmable over USB.  No
   other hardware is required.  This also means EVERYONE has the same
   programming hardware so the software can hide the fact that it is even
   being used.  No "settings" to figure out

2. The IDE is written in Java and is portable.  It is truly identical on
   all platforms.  Yes it uses gcc but the end user never has to deal with gcc
   or even know what gcc is.  Same with saving your code, hit just puts it
   "some place" and keeps track of it

3. There is a library of functions that work together.  and the library is
   the SAME on even Arduino so all the example code "just works".  you can cut
   and paste code between projects.  Most people when they write programs are
   really stringing together library calls.  So it takes two lines of code to
   get the value from an ADC and send it over USB to a PC.

4. There are lot of books and on-line training materials and all the
   examples work on all platforms and on all Arduino compatible devices.

5. it is fast.  I can change a line of code and then hit the "load" button
   and seconds later the changed code is running on the Arduino.  It is almost
   like programming an interpreted language

6. The whole system was designed so that artists and designers could us
   microcontrollersin their projects.    The first test project I did was to
   read the voltage from the wiper on a 100K pot and display it on an LCD
   screen.  It took a little over an hour and that included wiring up the
   hardware, plugging the Arduino into the computer.  Then I unplug the USB
   cable and connect a 9V battery and I have a portable toy project.

Chris Albertson
Redondo Beach, California

Chris,

Your undying devotion to the Arduino is laudable.  However, the point that i
think you are missing is such functionality is also available on other platforms
with the same amount of ease and support.  If you take someone who has never
seen, touched nor had any knowledge of any computing process, then you would find
that they would have just as much beginning trouble with the Arduino as any other
platform.

A true computer NERD would have the ability to flexibly deal with different
platforms, as each have their strengths and weaknesses.  Thus no one platform is
perfect and you chose the one that best fits the project.

Bill....WB6BNQ

Chris Albertson wrote:

On Wed, Apr 25, 2012 at 4:24 PM, WB6BNQ wb6bnq@cox.net wrote:

No, some platforms are harder than others.  Building an FPGA powered
project at home is harder than writing a Perl script.  Using a bare AVR
chip is harder then using the same chip inside an Arduino.  Try listing all
the skills one must learn to make an LED blink on various platforms.

You are correct about no platform being perfect.  Arduio is not well suited
to anything that you are going to manufacture.  The unit cost and size are
both 10X to high and it lacks enough power for things like signal
processing.  It is well suited to building one off projects that don't
require much compute power.

It's advantage is that it makes uP development slightly easier than writing
a Perl script.  The user does not need to know much.

I've used all kinds of computers,  Mainframe machines to control radars and
uPs to control head movement on a disk drive and I used a Linux system once
inside a CCD camera.

In this case I thought if the PicTic were to be redone I'd like for it to
be "hackable" by beginners who don't know a lot about TICs or uPs.  If you
make it to complex people will see it as a black box

--

Chris Albertson
Redondo Beach, California

That's a new one to me!  I expected them to be in Idaho, though.

-Dave

----- Original Message -----

From: "Daniel Mendes" dmendesf@gmail.com
To: "Discussion of precise time and frequency measurement" time-nuts@febo.com
Sent: Wednesday, April 25, 2012 3:17:43 PM
Subject: Re: [time-nuts] PICTIC II ready-made?

About replacing the 74ACT175... there´s a company called "Potato Semi"
(well.. they make "chips", right?) whose sole business is to make damn
fast 74 logic. Their chips can be bought at ebay in small quantities.
Look at this 600MHz D flip flop:

http://www.potatosemi.com/potatosemiweb/datasheet/PO74G74A.pdf

Daniel

Em 25/04/2012 16:15, Bruce Griffiths escreveu:

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Their technology paper talks a lot about differential inputs and
outputs but their 74G series is naturally all single ended.  They also
discuss using multiple bond wires to reduce inductance so maybe that
was all that was needed.

They sell through an Ebay store but given the price of $3 per chip and
$2 for shipping and handling, I would be inclined to design with
readily available ECL which is not much more expensive.

On Wed, 25 Apr 2012 19:17:43 -0300, Daniel Mendes dmendesf@gmail.com
wrote:

On Wed, 25 Apr 2012 11:13:42 -0700, Chris Albertson
albertson.chris@gmail.com wrote:

One problem with the design in this case is that it requires 8 or 9
I/O pins making the use of additional Arduino shields difficult. Would
you add tri-state buffering and a chip select?

On Wed, 25 Apr 2012 21:26:25 +0200, Attila Kinali attila@kinali.ch
wrote:

If you add a second lower current source or sink, then you can get
away with a LM311 class comparator and one fast timer channel in the
microcontroller.  The input pulse width charges the capacitor and the
timer counts how long it takes to slowly discharge.  Since the
conversion is integrating instead of sampling, it has better noise
immunity.

The Tektronix 2440 uses this technique to get about 50ps resolution.

On Wed, 25 Apr 2012 19:17:43 -0300
Daniel Mendes dmendesf@gmail.com wrote:

Hmm... looks interesting. Though, i probably would take
standard ECL instead of those because of higher availability
(you can get them from mouser, digikey & co).

But good to know that at least someone is still trying to improve
standard 74xx devices, for all those who do not want to use an CPLD/FPGA.

		Attila Kinali

--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin

On Fri, 27 Apr 2012 15:52:33 +0200, Attila Kinali attila@kinali.ch
wrote:

I would like to see some real world test results.  They charge $3 per
74G chip plus shipping through their Ebay store so the total price is
not much lower than ECL from Mouser or Digikey.

I have been going through various papers plus the Xilinx and Altera
forums reading about time delay counter design in connection with a
project I am working on involving equivalent time and high bandwidth
sampling.  One of the problems they have with the FPGA and CPLD
designs in significant input jitter even before the delay time chain
is considered.  For best results, all I/Os and other functions have to
be inactive during the measurement.  One of the papers discussed
disabling the LED heartbeat indicator to gain about 50ps of accuracy.

On Wed, 25 Apr 2012 23:30:45 -0500
David davidwhess@gmail.com wrote:

Yes, a dual slope time strecher would work too. I'm not sure, but
i would guess this aproach would be a lot more limited by the noise
and device variations.

Usually a timing input of an uC runs with a counter in the region
of 100MHz max, ie +/-5ns resolution. To get to 50ps, one would need
to stretch it by a factor of 100 at least, better 1000 to get some
headroom for calibration in software. This means that the currents
have to have a factor of 1000 in between. Using a charge current
somewhere between 10 to 100mA would yield to a discharge current
between 10 to 100uA. Keeping the two current sources stabile
enough for the ratio to stay stable would be already quite an
acheivment. Also keeping the leakage currents at bay would be
quite some feat...

In contrast to that, a 16bit ADC is dirty cheap and a 24bits are readily
available. I haven't had a look at it yet, but if the capacitive charge
redistribution ADCs simplifiy the circuitry that much as Bruce has said, then
you could get "easily" 16-18bit resolution. Combine that with a 100MHz
reference clock, then you get a nominal resolution 150-40fs(!).
Acheiving 10ps resolution should be then a piece of cake and 1ps possible.
(yes, i know that 10ps is not that easy...)

		Attila Kinali

PS: please correct me if i made a wrong assumption somewhere

--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin

Several practical replacements were provided if the 74ac175 dip was
impossible to find, see the wiki :
http://ko4bb.com/dokuwiki/doku.php?id=precision_timing:pictic

The issue was the voltage level of on and off  not the speed of the chip,
one goal of the project was to keep the interpolators as simple as possible
and to use the PIC as much as possible. So the design has several options:
no interpolators, interpolators with and without the 2x gain buffer, plus
the option of a faster clock speed as a way to reduce the need for
interpolators.

TICs, many more than any other way.

Stanley

From: "David" davidwhess@gmail.com
To: "Discussion of precise time and frequency measurement"
time-nuts@febo.com
Sent: Friday, April 27, 2012 9:22 AM
Subject: Re: [time-nuts] PICTIC II ready-made?

On Fri, 27 Apr 2012 15:52:33 +0200, Attila Kinali attila@kinali.ch
wrote:

I would like to see some real world test results.  They charge $3 per
74G chip plus shipping through their Ebay store so the total price is
not much lower than ECL from Mouser or Digikey.

I have been going through various papers plus the Xilinx and Altera
forums reading about time delay counter design in connection with a
project I am working on involving equivalent time and high bandwidth
sampling.  One of the problems they have with the FPGA and CPLD
designs in significant input jitter even before the delay time chain
is considered.  For best results, all I/Os and other functions have to
be inactive during the measurement.  One of the papers discussed
disabling the LED heartbeat indicator to gain about 50ps of accuracy.

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Hi

The ADC input is not quite perfect. There are the usual lumps of inductance
here and there and leakage. There's also a bit of a temperature coefficient
to the capacitance and some minor voltage dependencies. I think it's likely
that your best approach would wind up with something like "external NPO cap

• ADC" rather than just the ADC input. Still it's a cheap / easy thing to
  do.

If you charge with a current around 10 ma, and run a 20 ns max pulse width,
that gives you a capacitance of about 60 pf. Running up to 100 ma is
certainly possible.

Even if the net result is "only" 12 bits from a 16 bit part, that's still
quite good. Of course the real appeal would be to take a 10 bit (often
called 12, but they lie) ADC on a uC and maybe get 8 bits from it. If you
can start from a 10 to 20 ns pulse, that gets you to below 10 ps.

Bob

-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Attila Kinali
Sent: Friday, April 27, 2012 10:30 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] PICTIC II ready-made?

On Wed, 25 Apr 2012 23:30:45 -0500
David davidwhess@gmail.com wrote:

Yes, a dual slope time strecher would work too. I'm not sure, but
i would guess this aproach would be a lot more limited by the noise
and device variations.

Usually a timing input of an uC runs with a counter in the region
of 100MHz max, ie +/-5ns resolution. To get to 50ps, one would need
to stretch it by a factor of 100 at least, better 1000 to get some
headroom for calibration in software. This means that the currents
have to have a factor of 1000 in between. Using a charge current
somewhere between 10 to 100mA would yield to a discharge current
between 10 to 100uA. Keeping the two current sources stabile
enough for the ratio to stay stable would be already quite an
acheivment. Also keeping the leakage currents at bay would be
quite some feat...

In contrast to that, a 16bit ADC is dirty cheap and a 24bits are readily
available. I haven't had a look at it yet, but if the capacitive charge
redistribution ADCs simplifiy the circuitry that much as Bruce has said,
then
you could get "easily" 16-18bit resolution. Combine that with a 100MHz
reference clock, then you get a nominal resolution 150-40fs(!).
Acheiving 10ps resolution should be then a piece of cake and 1ps possible.
(yes, i know that 10ps is not that easy...)

		Attila Kinali

PS: please correct me if i made a wrong assumption somewhere

--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

On Fri, 27 Apr 2012 16:30:11 +0200, Attila Kinali attila@kinali.ch
wrote:

It would be a lot more immune to noise.  Both integrating and sampling
designs suffer from the same device variations which can be removed
through self calibration.

That is about the performance level of the Tektronix 2440 delay time
counter.  The counter only runs at 40 MHz but both edges of the 500
MHz sampling clock are used with two integrators so that metastability
can be detected and resolved.  The charge current is fixed at about
25mA and the discharge current is set during self calibration to
maintain a 1250:1 ratio at about 20uA.

Stability should not be a problem in the analog design when self
calibration is used and that is required at higher performance levels
anyway.  Even the high offset voltage and bias current of the bipolar
technology LM311 only contributes offset and gain error which is how
they got away with 100pf of integration capacitance.

Charge redistribution ADCs by design have a built in sample and hold
which can simplify external circuitry and like delta-sigma converters,
they can be built on a digital logic process.  In this case, the
simplification is in comparison to non-sampling converters where the
signal level has to be constant during the conversion cycle for valid
results.

The advantage with the dual slope design is that it is integrating so
high frequency noise is ignored.  Controlling noise in a
microcontroller sampling ADC even at the 10 bit level is a significant
challenge.  In a conservative design, I usually start by figuring the
loss of one bit do to DNL and another bit do to noise.  If you want
better performance, the ADC either needs to be integrating or external
where noise can be better controlled.

I have been looking at a better than 10ps performance design but not
primarily for GPS timing applications.  I am more interested in
equivalent time sampling and high bandwidth sequential or random time
sampling.  The later can not use an integrating converter because of
sampling rate requirements.

On Fri, 27 Apr 2012 10:19:17 -0500, "Stanley" timenuts@n4iqt.com
wrote:

I agree.

I apologize if my comments came across as criticisms of the PICTIC II
design.  My intention was to suggest possible alternatives and to
learn something in the discussion.

The Wilkinson TDC (dual slope) has been successfully used for decades in
nuclear instrumentation.
One problem is in switching the discharge current on and off
sufficiently quickly.
This can be largely circumvented by having it on all the time.
One drawback is the slow conversion speed (100us for a 10,000:1 ratio of
charge to discharge current).
However they can have superb differential linearity.

The problems associated with the jitter associated with an FPGA can be
circumvented by using external logic for the critical circuity
(synchroniser and current source gating).
Using a FET input comparator is advisable to avoid problems (linearity
and stability) associated with the comparator input bias current.

It may be feasible to implement the synchronisers in a small CPLD, but
careful selection to avoid those that use an internal preload state
machine whose clock runs continuously and not just during startup will
be required.

Bruce

David wrote:

By "preload" I think you mean the configuration step of the logic. It seems
that the Xilinx one stops the clock after the configuration is done. Anyway
using small EEPROM based CPLDs you have no clock at all: there is no
configuration to load.

On Fri, Apr 27, 2012 at 10:01 PM, Bruce Griffiths <
bruce.griffiths@xtra.co.nz> wrote:

On Sat, 28 Apr 2012 08:01:43 +1200, Bruce Griffiths
bruce.griffiths@xtra.co.nz wrote:

All of the designs I have looked at leave the discharge current turned
on.  The higher resolution ones adjust it during self calibration.

I prefer to use integrating converters (charge balancing, single
slope, dual slope, and delta-sigma) where possible because of their
noise rejection.

I actually looked into a GPSDO design using a charge balancing DAC to
drive the VCXO because of the low parts count and simplicity.  I still
may try it.

I had already concluded that the clock, trigger, and strobe paths need
to be outside the FPGA for minimum jitter.

I wonder if substituting an LF311 would be good enough.  I am inclined
to follow the integrator design from the Tektronix 7T11.

I will have to watch out for that.  Thanks for the warning.

One of the FPGA delay chain implementations I read about got down
below 50ps with heroic self calibration and mentioned that ANY I/O
activity during the measurement significantly reduced the accuracy.

On Fri, 27 Apr 2012 22:13:55 +0200, Azelio Boriani
azelio.boriani@screen.it wrote:

Wouldn't that also apply to an EEPROM based FPGA?  I have been
thinking that SRAM based devices may be a better match in cases where
you only want to have to program one device.

FPGA with internal flash memory to boot from, yes, but I think that small
CPLD haven't to boot anything: they should have the interconnection array
associated with the EEPROM cell array.

On Fri, Apr 27, 2012 at 11:52 PM, David davidwhess@gmail.com wrote:

Not true,  the configuration is loaded from EEPROM to RAM on power up.

Bruce

Azelio Boriani wrote:

I have not studied CPLDs but Actel has the only true Flash based FPGAs. The flash cells directly control the FPGA fabric. As such, they are mostly immune to Single Event Upset that plagues just about any other FPGA technology, and there is no configuration step at power up.

Didier KO4BB

Sent from my BlackBerry Wireless thingy while I do other things...

-----Original Message-----
From: Azelio Boriani azelio.boriani@screen.it
Sender: time-nuts-bounces@febo.com
Date: Sat, 28 Apr 2012 00:57:42
To: Discussion of precise time and frequency measurementtime-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] PICTIC II ready-made?

FPGA with internal flash memory to boot from, yes, but I think that small
CPLD haven't to boot anything: they should have the interconnection array
associated with the EEPROM cell array.

On Fri, Apr 27, 2012 at 11:52 PM, David davidwhess@gmail.com wrote:

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

On 4/28/12 12:10 PM, shalimr9@gmail.com wrote:

mmmm..  the flash contents can still be lost(although Actel claims that
their flash is pretty neutron and alpha particle immune.. but heavy
ions?)..  the Actel anti-fuse parts, like the AX and RTAX series, have
logic that can't be changed.  We use a lot of the Actel flash parts
(ProASIC3) for prototyping, then burn it to an rtax for final.

I think there's a similar path for the 54SX parts (i.e. a reprogrammable
version and an antifuse OTP part)

Here's what was in a Brookhaven report about using FPGAs in PHENIX

The Actel FPGAs do not have SRAM configuration memory so they are immune
to this form of upset.  FLASH memories exhibit dissipation of the charge
on the floating gate after 20kRad of integrated dose.  The dissipation
is not permanent damage and is remediated by reprogramming the device.
Flash memories also displayed SEE problems during programming during
radiation exposure that included gate punch-through, a destructive
effect.  These types of SEEs are avoided by not programming the FLASH
under radiation exposure conditions, namely during machine operation.

Practically speaking 20kRad is a fairly decent dose (it's a typical
design requirement for a trip to Mars or for GEO).. you pick up about a
kRad/year

In LEO it's a lot lower (otherwise astronauts in ISS would die).

Around Jupiter it's a lot higher (typical design requirements for Europa
missions and such are 1 MRad)

By the way, Actel is now part of Microsemi, with all that it entails.

Didier KO4BB

Sent from my BlackBerry Wireless thingy while I do other things...

-----Original Message-----
From: Jim Lux jimlux@earthlink.net
Sender: time-nuts-bounces@febo.com
Date: Sat, 28 Apr 2012 14:19:40
To: time-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] PICTIC II ready-made?

On 4/28/12 12:10 PM, shalimr9@gmail.com wrote:

mmmm..  the flash contents can still be lost(although Actel claims that
their flash is pretty neutron and alpha particle immune.. but heavy
ions?)..  the Actel anti-fuse parts, like the AX and RTAX series, have
logic that can't be changed.  We use a lot of the Actel flash parts
(ProASIC3) for prototyping, then burn it to an rtax for final.

I think there's a similar path for the 54SX parts (i.e. a reprogrammable
version and an antifuse OTP part)

Here's what was in a Brookhaven report about using FPGAs in PHENIX

The Actel FPGAs do not have SRAM configuration memory so they are immune
to this form of upset.  FLASH memories exhibit dissipation of the charge
on the floating gate after 20kRad of integrated dose.  The dissipation
is not permanent damage and is remediated by reprogramming the device.
Flash memories also displayed SEE problems during programming during
radiation exposure that included gate punch-through, a destructive
effect.  These types of SEEs are avoided by not programming the FLASH
under radiation exposure conditions, namely during machine operation.

Practically speaking 20kRad is a fairly decent dose (it's a typical
design requirement for a trip to Mars or for GEO).. you pick up about a
kRad/year

In LEO it's a lot lower (otherwise astronauts in ISS would die).

Around Jupiter it's a lot higher (typical design requirements for Europa
missions and such are 1 MRad)

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