WWVB BPSK Receiver Project?
Poul-Henning,
Do you need 16 bits or can you get by with a 12 bit ADC?
Have you considered using an FPGA for signal processing? It seems you need a fairly serious CPU to handle that much data.
Didier KO4BB
Sent from my BlackBerry Wireless thingy while I do other things...
-----Original Message-----
From: "Poul-Henning Kamp" phk@phk.freebsd.dk
Sender: time-nuts-bounces@febo.com
Date: Wed, 14 Mar 2012 22:16:38
To: Discussion of precise time and frequency measurementtime-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] WWVB BPSK Receiver Project?
In message 4F6116CE.7080809@pacific.net, Brooke Clarke writes:
I sure would like a WWVB BPSK receiver for the new modulation.
I've been playing with SDR and VLF signals for ages. What you
want is an antenna, a 1MSPS ADC and a fast-ish CPU.
One very interesting thing you can do with that, is to make a
buffer 1000 samples long, and continously average the received
signal into it, round-robin format.
That amounts to a comb-filter for every n1kHz signal, and a
trivial sin/cos multiplicator will give you the phase and
amplitude of every single radiotransmitter on n1kHz up to
your antialias filter at the same time.
If you have CPU power, you can also receive Loran-C by making the
buffer GRI*10 (or *20, if you want the code) samples long.
I've long thought about building a board with one of the faster
ARM CPUs and a 1MSPS 16bit ADC for this, but nobody else seemed
interested, so I've just used my hacked up rig.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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On Thu, 15 Mar 2012 13:50:08 +0000
shalimr9@gmail.com wrote:
Poul-Henning,
Do you need 16 bits or can you get by with a 12 bit ADC?
Have you considered using an FPGA for signal processing? It seems you need a fairly serious CPU to handle that much data.
I think Poul-Henning is refering to his AducLoran receiver, which
used a 1Msps ADC [1]. I dont remember what he exactly does with the signal,
but IIRC he uses a 40MHz uC which leaves him with 40 Cycles per sample,
which is quite a lot if you only do just some math calculation to detect
the start of a second...
And unlike with the FPGA, it does not take more time to process 8bit
or 24 bit samples as the uC works with 32bit numbers anyways.
Attila Kinali
[1] http://phk.freebsd.dk/AducLoran/
--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin
On 3/15/12 6:50 AM, shalimr9@gmail.com wrote:
Poul-Henning,
Do you need 16 bits or can you get by with a 12 bit ADC?
Have you considered using an FPGA for signal processing? It seems you need a fairly serious CPU to handle that much data.
You could use an FPGA, but the data rate isn't all that high. The
signal is fairly narrow band (<1 kHz, I should think). What you might
want to do is build a ADC/FPGA combo that provides a nice USB/Ethernet
interface for the sample stream which has been digital downconverted and
filtered. the FPGA takes care of the icky glue logic details and does
a bit of decimation.
Dear american colleagues,
as I read last few posts about WWVB, I am very tempted to return to LF
time signal fun. As I wrote you, there vere very good results using cheap
2 IC circuitry and a PC with our local DCF77 signal.
Under influence of this maillist, I am thinking about recreating of the
receiver using recent MCU, ferrite rod on one side, optional 10MHz input,
USB device acting as a standard USB audio class soundcard output.
Everything working with GNUradio, MATLAB, HAM waterfalls etc. out of the
box.
Could be used as an audio frequency front-end for HAM radio, too.
Would you be interested in such a kit? It should be <$100 all inclusive,
if there will be more people involved (let say 5-10) to cover PCBs.
Best regards,
Marek
Suppose the modulation is not present. The output of the phase detector
that steers the local standard ot indicator works correctly.
Now reverse the 60 kHz carrier. The phase detector works exactly thye
opposite way... wrong.
Now alternate between 0 and 190 degrees.
The loop alternate works between exactly right and exactly wrong... it
dithers around and the output is a measure of the ratio of 1's to 0's and
is utterly useless.
-John
============
On Wed, 14 Mar 2012 18:14:56 -0700
WB6BNQ wb6bnq@cox.net wrote:
His enthusiasm was aimed totally at new products. Although he admitted
it leaves all the real Timenut type people, actually
using the system for its intended purpose, out in the cold, he really
did not seem to care. Pointing out that a failure
with the GPS system left WWVB as the only alternate did not seem to
matter either.
Could someone be so kind and could explain me what the problem with
the BPSK modulation is? I mean the phase of WWVB shifts around several
10us
during sunrise/sunset already... Not to talk about the changing
propagation
conditions. Just see [1] for an example of what's happening.
Yes, for those devices that lock on the phase, you'd have to change
their correction/detection loop, but overall, they should still work.
Attila Kinali
[1] http://www.febo.com/time-freq/wwvb/spectracom/index.html
--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin
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Jim wrote:
a square wave,
multiplied by itself, has the same output as input.
Oh... I was assuming you had the two quadrature square waves (which are
just like the saturated LO for the mixer in RF land)
You don't have two square waves in quadrature. You have the (amplified)
signal from the antenna.
A Costas Loop recovers the bit stream and the carrier frequency (from
the local VCO) from a BPSK. It is self syncronizing.
Yes.. but if you don't care about the bitstream, and you want simpler
hardware, squaring works. (especially if the modulator doesn't have good
carrier suppression)
I think a better implementation would be:
Analog multiplier
Adaptive comparator (slice level = 1/2 P_P signal)
Flip Flop
Rabbit ears filter at 60 kHz
-John
=============
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On 3/15/12 7:49 AM, J. Forster wrote:
Suppose the modulation is not present. The output of the phase detector
that steers the local standard ot indicator works correctly.
Now reverse the 60 kHz carrier. The phase detector works exactly thye
opposite way... wrong.
Now alternate between 0 and 190 degrees.
The loop alternate works between exactly right and exactly wrong... it
dithers around and the output is a measure of the ratio of 1's to 0's and
is utterly useless.
and the cleverness of the Costas loop is that it uses (an estimate of)
the current data bit (the output of the I arm) to flip the sign of the
error signal from the quadrature arm.
There's a lot of scope for modification of the basic linear Costas loop.
Hard/soft limiters in either or both arms, you've got three filters
(the two arm filters and the loop filter) to fool with, plus all sorts
of schemes using "data aiding" where you get feedback from your symbol
slicer to help do a better job on the carrier tracking.
You can also run your loop with hard limited signal input (makes the
"mixers" turn into XOR gates).
If you don't need the bits in real time (i.e. you can tolerate some
latency), then you can also build tracking loops that effectively "look
into the future"; i.e. make decisions on carrier and bit at time t using
future data from t>now, as well as t=[-infinity, now].
Enormous literature out there on this, and it's been grist for many a
Master's or PhD dissertation.
All in a quest to get ever closer to the Shannon limit...
Why make it simple when complicated also works?
-John
============
On 3/15/12 7:49 AM, J. Forster wrote:
Suppose the modulation is not present. The output of the phase detector
that steers the local standard ot indicator works correctly.
Now reverse the 60 kHz carrier. The phase detector works exactly thye
opposite way... wrong.
Now alternate between 0 and 190 degrees.
The loop alternate works between exactly right and exactly wrong... it
dithers around and the output is a measure of the ratio of 1's to 0's
and
is utterly useless.
and the cleverness of the Costas loop is that it uses (an estimate of)
the current data bit (the output of the I arm) to flip the sign of the
error signal from the quadrature arm.
There's a lot of scope for modification of the basic linear Costas loop.
Hard/soft limiters in either or both arms, you've got three filters
(the two arm filters and the loop filter) to fool with, plus all sorts
of schemes using "data aiding" where you get feedback from your symbol
slicer to help do a better job on the carrier tracking.
You can also run your loop with hard limited signal input (makes the
"mixers" turn into XOR gates).
If you don't need the bits in real time (i.e. you can tolerate some
latency), then you can also build tracking loops that effectively "look
into the future"; i.e. make decisions on carrier and bit at time t using
future data from t>now, as well as t=[-infinity, now].
Enormous literature out there on this, and it's been grist for many a
Master's or PhD dissertation.
All in a quest to get ever closer to the Shannon limit...
time-nuts mailing list -- time-nuts@febo.com
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https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On Thu, 15 Mar 2012 07:49:15 -0700 (PDT)
"J. Forster" jfor@quikus.com wrote:
Suppose the modulation is not present. The output of the phase detector
that steers the local standard ot indicator works correctly.
Now reverse the 60 kHz carrier. The phase detector works exactly thye
opposite way... wrong.
Now alternate between 0 and 190 degrees.
The loop alternate works between exactly right and exactly wrong... it
dithers around and the output is a measure of the ratio of 1's to 0's and
is utterly useless.
That under the assumption, that they do not make sure that the average
phase is zeros out (or converges to 90°). I have not found anything
taht suggests this... on the other hand, there is nothing that suggests
the contrary either.
But you didnt address my main point yet: The phase of the WWVB signal
is already fluctuating a lot, just by natural occuring atmospherical
"noise". If a 180° phase shift does destabilize your PLL, what does
these "shifts" which are much larger do?
Attila Kinali
--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin
Hi
If you can handle the data rates for Loran at 100 KHz with a micro, then you
should be able to handle the data rates for something at 60 KHz. My guess is
that a simple "I know what the waveform is now compare it" approach would
not be terribly processor intensive. Put another way, you can easily predict
exactly what the signal will be doing at any instant. You just need to steer
to the error from that prediction.
Bob
-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Attila Kinali
Sent: Thursday, March 15, 2012 10:26 AM
To: shalimr9@gmail.com; Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] WWVB BPSK Receiver Project?
On Thu, 15 Mar 2012 13:50:08 +0000
shalimr9@gmail.com wrote:
Poul-Henning,
Do you need 16 bits or can you get by with a 12 bit ADC?
Have you considered using an FPGA for signal processing? It seems you need
a fairly serious CPU to handle that much data.
I think Poul-Henning is refering to his AducLoran receiver, which
used a 1Msps ADC [1]. I dont remember what he exactly does with the signal,
but IIRC he uses a 40MHz uC which leaves him with 40 Cycles per sample,
which is quite a lot if you only do just some math calculation to detect
the start of a second...
And unlike with the FPGA, it does not take more time to process 8bit
or 24 bit samples as the uC works with 32bit numbers anyways.
Attila Kinali
[1] http://phk.freebsd.dk/AducLoran/
--
The trouble with you, Shev, is you don't say anything until you've saved
up a whole truckload of damned heavy brick arguments and then you dump
them all out and never look at the bleeding body mangled beneath the heap
-- Tirin, The Dispossessed, U. Le Guin
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
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