Hello, I'm trying to achieve a constant phase offset with multiple X310s each using a UBX160 daughter card. My procedure is as follows: 1) All X310s have a 10MHz reference and PPS fed via an octoclock 2) each device FPGA time is aligned on the PPS edge 3) each device sets their LO to the same frequency at the same time using timed FPGA commands 4) each device transmits an orthogonal PN sequence using timed transmit and the phase of each is measured on a x310 which is also initialized using the previous procedure The behavior I have seen is that the phase difference between radios is constant only when using a low center frequency (tested on 40 MHz fc, 1 MHz Fs). At 2.4 GHz and 920 Mhz the phase drifts between runs. Does anyone have any insight into why this would be the case? Things I have tried: - Integer-n and fractional-n tuning - manual and automatic tuning policies The UHD version is source built 3.13.0 <https://github.com/EttusResearch/uhd/commit/f114cfa0ddf70228d10462758c2b8e878c993f5d> from git and I have rebuilt the FPGA image with these commits added: https://github.com/EttusResearch/fpga/commit/205747dee8e73ec15f521e9363337c8c03582d91 https://github.com/EttusResearch/fpga/commit/0b2364653405612a6d5dfaa0e69b1c6798771e6d I'm also going to try using the most up-to-date 3.14.1.0 release. Thanks, -- *Mitchell J Grabner, PhD* *Member, IEEE Communications Society* *IEEE-HKN Lambda Zeta Chapter* *------------------------------------------------* My Linkedin <http://www.linkedin.com/pub/mitch-grabner/43/23b/bb5>

On 07/31/2019 09:38 AM, Mitch Grabner via USRP-users wrote: > Hello, > > I'm trying to achieve a constant phase offset with multiple X310s each > using a UBX160 daughter card. My procedure is as follows: > 1) All X310s have a 10MHz reference and PPS fed via an octoclock > 2) each device FPGA time is aligned on the PPS edge > 3) each device sets their LO to the same frequency at the same time > using timed FPGA commands > 4) each device transmits an orthogonal PN sequence using timed > transmit and the phase of each is measured on a x310 which is also > initialized using the previous procedure > > The behavior I have seen is that the phase difference between radios > is constant only when using a low center frequency (tested on 40 MHz > fc, 1 MHz Fs). At 2.4 GHz and 920 Mhz the phase drifts between runs. > Does anyone have any insight into why this would be the case? > > Things I have tried: > - Integer-n and fractional-n tuning > - manual and automatic tuning policies > > The UHD version is source built 3.13.0|||| > <https://github.com/EttusResearch/uhd/commit/f114cfa0ddf70228d10462758c2b8e878c993f5d> > from git and I have rebuilt the FPGA image with these commits added: > https://github.com/EttusResearch/fpga/commit/205747dee8e73ec15f521e9363337c8c03582d91 > https://github.com/EttusResearch/fpga/commit/0b2364653405612a6d5dfaa0e69b1c6798771e6d > I'm also going to try using the most up-to-date 3.14.1.0 release. > > Thanks, > Let us know whether the 3.14.1.0 release helps. I'm a bit surprised by the problem showing up on the *higher* bands, because below 500MHz, there are TWO layers of synthesizers and mixers involved--you'd expect phase-coherence problems to be more likely in that case. The LOs have phase-reset features, which I'm fairly-sure are actually implemented. What is the magnitude of the phase offset in the high-band case?