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N310 RFNoC OOT Module Build Issue

Ramazan Çetin
Mon, Apr 15, 2019 1:03 PM

Hello,

I am trying to build basic OOT module for N310. My UHD version is
3.14.0.0-rc1 (I also tried with 3.14.0.0). I can build FPGA image
without OOT modules for N310. But when i try building with OOT module
using this command, it gives this error:

rcetin@rcetin-ThinkPad-W530:~/rfnoc/fpga/usrp3$ ./uhd_image_builder.py
gain -I /home/rcetin/rfnoc/rfnoc-gohm -d N310 -t N310_RFNOC_HG

--Using the following blocks to generate image:
    * gain
Adding CE instantiation file for 'N310_RFNOC_HG'
changing temporarily working directory to
/home/rcetin/rfnoc/fpga/usrp3/tools/scripts/../../top/n3xx
Setting up a 64-bit FPGA build environment for the USRP-N3x0...

  • Vivado: Found (/home/rcetin/opt/Xilinx/Vivado/2017.4/bin)

Environment successfully initialized.
make -f Makefile.n3xx.inc bin NAME=N310_RFNOC_HG ARCH=zynq
PART_ID=xc7z100/ffg900/-2 SFP0_1GBE=1   SFP1_10GBE=1 USE_REPLAY=1  
BUILD_1G=1     BUILD_10G=1     RFNOC=1 N310=1 TOP_MODULE=n3xx
EXTRA_DEFS="SFP0_1GBE=1   SFP1_10GBE=1 USE_REPLAY=1   BUILD_1G=1    
BUILD_10G=1     RFNOC=1 N310=1"
make[1]: Entering directory '/home/rcetin/rfnoc/fpga/usrp3/top/n3xx'
BUILDER: Checking tools...

  • GNU bash, version 4.4.19(1)-release (x86_64-pc-linux-gnu)
  • Python 2.7.15rc1
  • Vivado v2017.4 (64-bit)
    Using parser configuration from:
    /home/rcetin/rfnoc/fpga/usrp3/top/n3xx/dev_config.json
    [00:00:00] Executing command: vivado -mode batch -source
    /home/rcetin/rfnoc/fpga/usrp3/top/n3xx/build_n3xx.tcl -log build.log
    -journal n3xx.jou
    [00:00:01] Current task: Initialization +++ Current Phase: Starting

.

.

.

ERROR: [Synth 8-439] module 'noc_block_gain' not found
[/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v:22]
ERROR: [Synth 8-285] failed synthesizing module 'n3xx_core'
[/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-285] failed synthesizing module 'n3xx'
[/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
console or run log file for details
[00:07:18] Current task: Synthesis +++ Current Phase: Starting
[00:07:19] Current task: Synthesis +++ Current Phase: Finished
[00:07:19] Process terminated. Status: Failure

---=======================
Warnings:           322
Critical Warnings:  4
Errors:             4

Makefile.n3xx.inc:149: recipe for target 'bin' failed
make[1]: *** [bin] Error 1
make[1]: Leaving directory '/home/rcetin/rfnoc/fpga/usrp3/top/n3xx'
Makefile:133: recipe for target 'N310_RFNOC_HG' failed
make: *** [N310_RFNOC_HG] Error 2

This is my Makefile.OOT.inc

##################################################

Include OOT makefiles

##################################################

OOT_DIR = $(BASE_DIR)/../../../rfnoc-gohm/rfnoc
RFNOC_OOT_SRCS += $(addprefix
/home/rcetin/rfnoc/rfnoc-gohm/rfnoc/fpga-src/,
noc_block_gain.v
) \

I can build OOT modules for E310 but cannot for N310. Can you please
help to solve this problem?

Best regards.

Hello, I am trying to build basic OOT module for N310. My UHD version is 3.14.0.0-rc1 (I also tried with 3.14.0.0). I can build FPGA image without OOT modules for N310. But when i try building with OOT module using this command, it gives this error: rcetin@rcetin-ThinkPad-W530:~/rfnoc/fpga/usrp3$ ./uhd_image_builder.py gain -I /home/rcetin/rfnoc/rfnoc-gohm -d N310 -t N310_RFNOC_HG --Using the following blocks to generate image:     * gain Adding CE instantiation file for 'N310_RFNOC_HG' changing temporarily working directory to /home/rcetin/rfnoc/fpga/usrp3/tools/scripts/../../top/n3xx Setting up a 64-bit FPGA build environment for the USRP-N3x0... - Vivado: Found (/home/rcetin/opt/Xilinx/Vivado/2017.4/bin) Environment successfully initialized. make -f Makefile.n3xx.inc bin NAME=N310_RFNOC_HG ARCH=zynq PART_ID=xc7z100/ffg900/-2 SFP0_1GBE=1   SFP1_10GBE=1 USE_REPLAY=1   BUILD_1G=1     BUILD_10G=1     RFNOC=1 N310=1 TOP_MODULE=n3xx EXTRA_DEFS="SFP0_1GBE=1   SFP1_10GBE=1 USE_REPLAY=1   BUILD_1G=1     BUILD_10G=1     RFNOC=1 N310=1" make[1]: Entering directory '/home/rcetin/rfnoc/fpga/usrp3/top/n3xx' BUILDER: Checking tools... * GNU bash, version 4.4.19(1)-release (x86_64-pc-linux-gnu) * Python 2.7.15rc1 * Vivado v2017.4 (64-bit) Using parser configuration from: /home/rcetin/rfnoc/fpga/usrp3/top/n3xx/dev_config.json [00:00:00] Executing command: vivado -mode batch -source /home/rcetin/rfnoc/fpga/usrp3/top/n3xx/build_n3xx.tcl -log build.log -journal n3xx.jou [00:00:01] Current task: Initialization +++ Current Phase: Starting . . . ERROR: [Synth 8-439] module 'noc_block_gain' not found [/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/rfnoc_ce_auto_inst_n310.v:22] ERROR: [Synth 8-285] failed synthesizing module 'n3xx_core' [/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/n3xx_core.v:17] ERROR: [Synth 8-285] failed synthesizing module 'n3xx' [/home/rcetin/rfnoc/fpga/usrp3/top/n3xx/dboards/mg/n3xx.v:13] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details [00:07:18] Current task: Synthesis +++ Current Phase: Starting [00:07:19] Current task: Synthesis +++ Current Phase: Finished [00:07:19] Process terminated. Status: Failure ======================================================== Warnings:           322 Critical Warnings:  4 Errors:             4 Makefile.n3xx.inc:149: recipe for target 'bin' failed make[1]: *** [bin] Error 1 make[1]: Leaving directory '/home/rcetin/rfnoc/fpga/usrp3/top/n3xx' Makefile:133: recipe for target 'N310_RFNOC_HG' failed make: *** [N310_RFNOC_HG] Error 2 This is my Makefile.OOT.inc ################################################## # Include OOT makefiles ################################################## OOT_DIR = $(BASE_DIR)/../../../rfnoc-gohm/rfnoc RFNOC_OOT_SRCS += $(addprefix /home/rcetin/rfnoc/rfnoc-gohm/rfnoc/fpga-src/, \ noc_block_gain.v \ ) \ I can build OOT modules for E310 but cannot for N310. Can you please help to solve this problem? Best regards.