usrp-users@lists.ettus.com
Discussion and technical support related to USRP, UHD, RFNoC
View all threadsunderstanding rfnocmodtool
Just started working on trying to use rfnocmodtool. I started creating
a block and did the usual:
mkdir build
cd build
cmake -DCMAKE_INSTALL_PREFIX=~/pybombs ../
make && make install
That seems to do everything I think it should do with the gnuradio. The
thing I am unsure of, is how to have it "place" the verilog files in the
proper directories. Is there a command I am missing for that?
Also, if I want to use a core in a module, is there anyway to build it
from within the rfnocblock module of interest folder? Or do I have to
go to the normal usrp3_rfnoc/top/x310 and do a make GUI=1 like we used to?
Hello Jason,
when you add a block with the command "rfnocmodtool add {your_block_name}",
a verilog template for your file should have been created at the
{OOT_DIR}/rfnoc/fpga-src/ folder. Aren't they being generated there?
It they are, and you want to create a fpga.bit with this files, you can do
so by using the make.py script and the procedure depicted in the tutorial
here:
https://kb.ettus.com/Getting_Started_with_RFNoC_Development#Building_the_FPGA_image.
You don't necessarily have to move the location of your files.
Could you be more specific to what are you referring as "core", I'm not
quite sure on how to answer that part of your inquiry.
Cheers,
-Nicolas
On Fri, Aug 26, 2016 at 10:35 AM, Jason Matusiak via USRP-users <
usrp-users@lists.ettus.com> wrote:
Just started working on trying to use rfnocmodtool. I started creating a
block and did the usual:
mkdir build
cd build
cmake -DCMAKE_INSTALL_PREFIX=~/pybombs ../
make && make install
That seems to do everything I think it should do with the gnuradio. The
thing I am unsure of, is how to have it "place" the verilog files in the
proper directories. Is there a command I am missing for that?
Also, if I want to use a core in a module, is there anyway to build it
from within the rfnocblock module of interest folder? Or do I have to go
to the normal usrp3_rfnoc/top/x310 and do a make GUI=1 like we used to?
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Thank you for the quick reply Nicolas. I will take a look at the
make.py and see how it plays in. I guess I expected some script to
/move/ the Xilinx files into your directory, that is nice that it can
stay within the newly made one.
The cores I was referring to was the Xilinx build-in cores that can be
utilized from within RFNoC modules (like CORDIC, FFT, etc.). With the
old method, we had to create the cores in a splintered project and then
move them into the ip directory withing lib. I was wondering if they
had to go anywhere specific now to be picked up from make.py?
Thanks!
On 08/26/2016 03:12 PM, Nicolas Cuervo wrote:
Hello Jason,
when you add a block with the command "rfnocmodtool add
{your_block_name}", a verilog template for your file should have been
created at the {OOT_DIR}/rfnoc/fpga-src/ folder. Aren't they being
generated there?
It they are, and you want to create a fpga.bit with this files, you
can do so by using the make.py script and the procedure depicted in
the tutorial here:
https://kb.ettus.com/Getting_Started_with_RFNoC_Development#Building_the_FPGA_image.
You don't necessarily have to move the location of your files.
Could you be more specific to what are you referring as "core", I'm
not quite sure on how to answer that part of your inquiry.
Cheers,
-Nicolas
On Fri, Aug 26, 2016 at 10:35 AM, Jason via USRP-users
<usrp-users@lists.ettus.com mailto:usrp-users@lists.ettus.com> wrote:
Just started working on trying to use rfnocmodtool. I started
creating a block and did the usual:
mkdir build
cd build
cmake -DCMAKE_INSTALL_PREFIX=~/pybombs ../
make && make install
That seems to do everything I think it should do with the
gnuradio. The thing I am unsure of, is how to have it "place" the
verilog files in the proper directories. Is there a command I am
missing for that?
Also, if I want to use a core in a module, is there anyway to
build it from within the rfnocblock module of interest folder? Or
do I have to go to the normal usrp3_rfnoc/top/x310 and do a make
GUI=1 like we used to?
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
<http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com>
Hello Jason,
The explicit integration of XiIlinx IP into a newly created block, although
we have that in mind, is still not provided. The tools so far intend to
ease the cumbersome steps of getting a RFNoC block running. We expect to
add further functionalities in the future!
However, keep in mind that given that the build of the fpga image will
still take place in usrp3_rfnoc/top/{x300|e300}/build*,your block will have
access to the built IPs that you have in the given target directory. This
means that, even though you save some steps using the new utilities, you'd
have to do the same process you followed before if you add/modify an IP.
I hope this answer your question.
Cheers,
-N
On Tue, Aug 30, 2016 at 9:20 AM, Jason Matusiak <
jason@gardettoengineering.com> wrote:
Thank you for the quick reply Nicolas. I will take a look at the make.py
and see how it plays in. I guess I expected some script to move the
Xilinx files into your directory, that is nice that it can stay within the
newly made one.
The cores I was referring to was the Xilinx build-in cores that can be
utilized from within RFNoC modules (like CORDIC, FFT, etc.). With the old
method, we had to create the cores in a splintered project and then move
them into the ip directory withing lib. I was wondering if they had to go
anywhere specific now to be picked up from make.py?
Thanks!
On 08/26/2016 03:12 PM, Nicolas Cuervo wrote:
Hello Jason,
when you add a block with the command "rfnocmodtool add
{your_block_name}", a verilog template for your file should have been
created at the {OOT_DIR}/rfnoc/fpga-src/ folder. Aren't they being
generated there?
It they are, and you want to create a fpga.bit with this files, you can do
so by using the make.py script and the procedure depicted in the tutorial
here: https://kb.ettus.com/Getting_Started_with_RFNoC_
Development#Building_the_FPGA_image. You don't necessarily have to move
the location of your files.
Could you be more specific to what are you referring as "core", I'm not
quite sure on how to answer that part of your inquiry.
Cheers,
-Nicolas
On Fri, Aug 26, 2016 at 10:35 AM, Jason via USRP-users <
usrp-users@lists.ettus.com> wrote:
Just started working on trying to use rfnocmodtool. I started creating a
block and did the usual:
mkdir build
cd build
cmake -DCMAKE_INSTALL_PREFIX=~/pybombs ../
make && make install
That seems to do everything I think it should do with the gnuradio. The
thing I am unsure of, is how to have it "place" the verilog files in the
proper directories. Is there a command I am missing for that?
Also, if I want to use a core in a module, is there anyway to build it
from within the rfnocblock module of interest folder? Or do I have to go
to the normal usrp3_rfnoc/top/x310 and do a make GUI=1 like we used to?
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com