When I run the gain example testbench file I am faced with errors.....How can I solve this? Vivado Simulator does not support tracing of System Verilog Dynamic Type object. ======================================================== TESTBENCH STARTED: rfnoc_block_gain_tb ======================================================== [TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it... *Fatal: Timeout: Test "Flush block then reset it" time limit exceeded*Time: 10 us Iteration: 0 Process: /PkgTestExec/TestExec::start_timeout/Block260_9/timeout File: /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv $finish called at time : 10 us : File "/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv" Line 235 INFO: [USF-XSim-96] XSim completed. Design snapshot 'rfnoc_block_gain_tb_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000000000us launch_simulation: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1462.531 ; gain = 80.324 ; free physical = 285 ; free virtual = 9898 # if { [info exists ::env(VIV_SYNTH_TOP)] } { # puts "BUILDER: Synthesizing" # # Synthesize requested modules # foreach synth_top "$::env(VIV_SYNTH_TOP)" { # set_property top $synth_top [current_fileset] # synth_design -mode out_of_context # # Perform a simple regex-based search for all clock signals and constrain # # them to 500 MHz for the timing report. # set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*" # foreach clk_inst [get_ports -regexp $clk_regexp] { # create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst] # } # report_utilization -no_primitives -file ${working_dir}/${synth_top}_synth.rpt # report_timing_summary -setup -max_paths 3 -unique_pins -no_header -append -file ${working_dir}/${synth_top}_synth.rpt # write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp # } # } else { # puts "BUILDER: Skipping resource report because VIV_SYNTH_TOP is not set" # } BUILDER: Synthesizing # if [string equal $vivado_mode "batch"] { # puts "BUILDER: Closing project" # close_project # } else { # puts "BUILDER: In GUI mode. Leaving project open." # } BUILDER: Closing project INFO: [Common 17-206] Exiting Vivado at Thu Feb 10 10:02:45 2022... make[4]: warning: Clock skew detected. Your build may be incomplete. make[3]: warning: Clock skew detected. Your build may be incomplete. Built target rfnoc_block_gain_tb make[2]: warning: Clock skew detected. Your build may be incomplete. make[1]: warning: Clock skew detected. Your build may be incomplete. make: warning: Clock skew detected. Your build may be incomplete.

The unmodified gain example should work, so I assume you modified it or are trying your own version. I suggest you look at the example to see what you did differently. https://github.com/EttusResearch/uhddev/tree/master/host/examples/rfnoc-example/fpga/rfnoc_block_gain The simulator is the tool designed for debugging issues with code. So you might look into the Xilinx documentation on how to use the simulator. The UHD manual has instructions on how to run testbenches and load the simulation in the Vivado GUI. My guess is that you have a signal that's not connected correctly, like a clock or reset. Wade On Tue, Apr 5, 2022 at 12:42 AM sp h <stackprogramer@gmail.com> wrote: > When I run the gain example testbench file I am faced with errors.....How > can I solve this? > > > Vivado Simulator does not support tracing of System Verilog Dynamic Type > object. > ======================================================== > TESTBENCH STARTED: rfnoc_block_gain_tb > ======================================================== > [TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it... > > *Fatal: Timeout: Test "Flush block then reset it" time limit exceeded*Time: > 10 us Iteration: 0 Process: > /PkgTestExec/TestExec::start_timeout/Block260_9/timeout File: > /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv > $finish called at time : 10 us : File > "/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv" Line > 235 > INFO: [USF-XSim-96] XSim completed. Design snapshot > 'rfnoc_block_gain_tb_behav' loaded. > INFO: [USF-XSim-97] XSim simulation ran for 1000000000us > launch_simulation: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory > (MB): peak = 1462.531 ; gain = 80.324 ; free physical = 285 ; free virtual > = 9898 > # if { [info exists ::env(VIV_SYNTH_TOP)] } { > # puts "BUILDER: Synthesizing" > # # Synthesize requested modules > # foreach synth_top "$::env(VIV_SYNTH_TOP)" { > # set_property top $synth_top [current_fileset] > # synth_design -mode out_of_context > # # Perform a simple regex-based search for all clock signals and > constrain > # # them to 500 MHz for the timing report. > # set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*" > # foreach clk_inst [get_ports -regexp $clk_regexp] { > # create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst] > # } > # report_utilization -no_primitives -file > ${working_dir}/${synth_top}_synth.rpt > # report_timing_summary -setup -max_paths 3 -unique_pins -no_header > -append -file ${working_dir}/${synth_top}_synth.rpt > # write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp > # } > # } else { > # puts "BUILDER: Skipping resource report because VIV_SYNTH_TOP is not > set" > # } > BUILDER: Synthesizing > # if [string equal $vivado_mode "batch"] { > # puts "BUILDER: Closing project" > # close_project > # } else { > # puts "BUILDER: In GUI mode. Leaving project open." > # } > BUILDER: Closing project > INFO: [Common 17-206] Exiting Vivado at Thu Feb 10 10:02:45 2022... > make[4]: warning: Clock skew detected. Your build may be incomplete. > make[3]: warning: Clock skew detected. Your build may be incomplete. > Built target rfnoc_block_gain_tb > make[2]: warning: Clock skew detected. Your build may be incomplete. > make[1]: warning: Clock skew detected. Your build may be incomplete. > make: warning: Clock skew detected. Your build may be incomplete. > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >

Thanks, I edited the gain files now it works. All test was passed. Vivado Simulator does not support tracing of System Verilog Dynamic Type object. ======================================================== TESTBENCH STARTED: chdr_crossbar_nxn: IP_OPTION = HDL_IP ======================================================== [TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it... [TEST CASE 1] (t = 6450 ns) DONE... Passed [TEST CASE 2] (t = 6450 ns) BEGIN: Verify Block Info... [TEST CASE 2] (t = 6450 ns) DONE... Passed [TEST CASE 3] (t = 6450 ns) BEGIN: Verify gain register... [TEST CASE 3] (t = 7875 ns) DONE... Passed [TEST CASE 4] (t = 7875 ns) BEGIN: Test gain of 1... [TEST CASE 4] (t = 8920 ns) DONE... Passed [TEST CASE 5] (t = 8920 ns) BEGIN: Test gain of -1... [TEST CASE 5] (t = 9900 ns) DONE... Passed [TEST CASE 6] (t = 9900 ns) BEGIN: Test gain of 0... [TEST CASE 6] (t = 10975 ns) DONE... Passed [TEST CASE 7] (t = 10975 ns) BEGIN: Test gain of 37... [TEST CASE 7] (t = 12020 ns) DONE... Passed [TEST CASE 8] (t = 12020 ns) BEGIN: Test gain of -22... [TEST CASE 8] (t = 13140 ns) DONE... Passed [TEST CASE 9] (t = 13140 ns) BEGIN: Test gain of 256... [TEST CASE 9] (t = 14300 ns) DONE... Passed ======================================================== TESTBENCH FINISHED: chdr_crossbar_nxn: IP_OPTION = HDL_IP - Time elapsed: 14300 ns - Tests Run: 9 - Tests Passed: 9 - Tests Failed: 0 Result: PASSED On Wed, Apr 6, 2022 at 1:43 AM Wade Fife <wade.fife@ettus.com> wrote: > The unmodified gain example should work, so I assume you modified it or > are trying your own version. I suggest you look at the example to see what > you did differently. > > > https://github.com/EttusResearch/uhddev/tree/master/host/examples/rfnoc-example/fpga/rfnoc_block_gain > > The simulator is the tool designed for debugging issues with code. So you > might look into the Xilinx documentation on how to use the simulator. The > UHD manual has instructions on how to run testbenches and load the > simulation in the Vivado GUI. > > My guess is that you have a signal that's not connected correctly, like a > clock or reset. > > Wade > > On Tue, Apr 5, 2022 at 12:42 AM sp h <stackprogramer@gmail.com> wrote: > >> When I run the gain example testbench file I am faced with errors.....How >> can I solve this? >> >> >> Vivado Simulator does not support tracing of System Verilog Dynamic Type >> object. >> ======================================================== >> TESTBENCH STARTED: rfnoc_block_gain_tb >> ======================================================== >> [TEST CASE 1] (t = 0 ns) BEGIN: Flush block then reset it... >> >> *Fatal: Timeout: Test "Flush block then reset it" time limit exceeded*Time: >> 10 us Iteration: 0 Process: >> /PkgTestExec/TestExec::start_timeout/Block260_9/timeout File: >> /home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv >> $finish called at time : 10 us : File >> "/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/sim/rfnoc/PkgTestExec.sv" Line >> 235 >> INFO: [USF-XSim-96] XSim completed. Design snapshot >> 'rfnoc_block_gain_tb_behav' loaded. >> INFO: [USF-XSim-97] XSim simulation ran for 1000000000us >> launch_simulation: Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory >> (MB): peak = 1462.531 ; gain = 80.324 ; free physical = 285 ; free virtual >> = 9898 >> # if { [info exists ::env(VIV_SYNTH_TOP)] } { >> # puts "BUILDER: Synthesizing" >> # # Synthesize requested modules >> # foreach synth_top "$::env(VIV_SYNTH_TOP)" { >> # set_property top $synth_top [current_fileset] >> # synth_design -mode out_of_context >> # # Perform a simple regex-based search for all clock signals and >> constrain >> # # them to 500 MHz for the timing report. >> # set clk_regexp "(?i)^(?!.*en.*).*(clk|clock).*" >> # foreach clk_inst [get_ports -regexp $clk_regexp] { >> # create_clock -name $clk_inst -period 2.0 [get_ports $clk_inst] >> # } >> # report_utilization -no_primitives -file >> ${working_dir}/${synth_top}_synth.rpt >> # report_timing_summary -setup -max_paths 3 -unique_pins -no_header >> -append -file ${working_dir}/${synth_top}_synth.rpt >> # write_checkpoint -force ${working_dir}/${synth_top}_synth.dcp >> # } >> # } else { >> # puts "BUILDER: Skipping resource report because VIV_SYNTH_TOP is not >> set" >> # } >> BUILDER: Synthesizing >> # if [string equal $vivado_mode "batch"] { >> # puts "BUILDER: Closing project" >> # close_project >> # } else { >> # puts "BUILDER: In GUI mode. Leaving project open." >> # } >> BUILDER: Closing project >> INFO: [Common 17-206] Exiting Vivado at Thu Feb 10 10:02:45 2022... >> make[4]: warning: Clock skew detected. Your build may be incomplete. >> make[3]: warning: Clock skew detected. Your build may be incomplete. >> Built target rfnoc_block_gain_tb >> make[2]: warning: Clock skew detected. Your build may be incomplete. >> make[1]: warning: Clock skew detected. Your build may be incomplete. >> make: warning: Clock skew detected. Your build may be incomplete. >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-leave@lists.ettus.com >> >