component trace is
  port(
       	clk         : in std_logic;
       	begin_inst  : in std_logic;
       	pc          : in std_logic_vector(maxAddrBitIncIO downto 0);
		opcode		: in std_logic_vector(7 downto 0);
		sp			: in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
		memA		: in std_logic_vector(wordSize-1 downto 0);
		memB		: in std_logic_vector(wordSize-1 downto 0);
		busy         : in std_logic;
		intSp		: in std_logic_vector(stack_bits-1 downto 0)
		);
end component;

Derrick, You used the correct command line but I had failed to guess you were using Windows not Linux. I have to confess I rarely use windows, and never for GNUradio and USRP. All Xilinx work and testing of FPGA builds at Ettus is done under linux only. Under windows it *might* be possible to use the make based methodology if Cygwin was installed to provide a unix like command line but I certainly couldn't promise you that. So back to your original question about the trace module, maybe we can still get you running using the ISE GUI: I notice that the component for "trace" doesn't actually declare any outputs, and that it's called from a generate conditionally ....I'm going to guess that this is a simulation debug option to dump verbosely to a file used during ZPU development and that "Generate_Trace" is not defined in a normal USRP build, hence the trace component is never included in the design. That's just a hypothesis, you'll have to confirm that, but clearly it wouldn't do anything of any practical use in the FPGA. -Ian On Jul 11, 2012, at 12:53 AM, Derrick Ho wrote: > Hello Ian > > I've looked inside those files and could not find the implementation of the "trace" module. > > I'm not entirely sure what to do with the makefile so I took a guess and tried running the make file in the > xilinx command prompt. I got this error message > > C:\Documents and Settings\Administrator\My Documents\Source_code_of_uhd\fpga\usr > p2\top\N2x0>make N210R4 > make -f Makefile.N210R4 bin > make[1]: Entering directory `C:/Documents and Settings/Administrator/My Document > s/Source_code_of_uhd/fpga/usrp2/top/N2x0' > ../Makefile.common:57: warning: overriding commands for target `C:/Documents' > ../Makefile.common:53: warning: ignoring old commands for target `C:/Documents' > ../Makefile.common:57: warning: overriding commands for target `and' > ../Makefile.common:53: warning: ignoring old commands for target `and' > ../Makefile.common:57: warning: overriding commands for target `Settings/Adminis > trator/My' > ../Makefile.common:53: warning: ignoring old commands for target `Settings/Admin > istrator/My' > ../Makefile.common:62: warning: overriding commands for target `C:/Documents' > ../Makefile.common:57: warning: ignoring old commands for target `C:/Documents' > ../Makefile.common:62: warning: overriding commands for target `and' > ../Makefile.common:57: warning: ignoring old commands for target `and' > ../Makefile.common:62: warning: overriding commands for target `Settings/Adminis > trator/My' > ../Makefile.common:57: warning: ignoring old commands for target `Settings/Admin > istrator/My' > make[1]: Circular C:/Documents <- C:/Documents dependency dropped. > make[1]: Circular and <- C:/Documents dependency dropped. > make[1]: Circular and <- and dependency dropped. > make[1]: Circular Settings/Administrator/My <- C:/Documents dependency dropped. > make[1]: Circular Settings/Administrator/My <- and dependency dropped. > make[1]: Circular Settings/Administrator/My <- Settings/Administrator/My depende > ncy dropped. > make[1]: Circular Documents/Source_code_of_uhd/fpga/usrp2/top/N2x0/build-N210R4/ > u2plus.bin <- C:/Documents dependency dropped. > make[1]: Circular Documents/Source_code_of_uhd/fpga/usrp2/top/N2x0/build-N210R4/ > u2plus.bin <- and dependency dropped. > make[1]: Circular Documents/Source_code_of_uhd/fpga/usrp2/top/N2x0/build-N210R4/ > u2plus.bin <- Settings/Administrator/My dependency dropped. > make[1]: Circular Documents/Source_code_of_uhd/fpga/usrp2/top/N2x0/build-N210R4/ > u2plus.xise <- C:/Documents dependency dropped. > make[1]: Circular Documents/Source_code_of_uhd/fpga/usrp2/top/N2x0/build-N210R4/ > u2plus.xise <- and dependency dropped. > make[1]: Circular Documents/Source_code_of_uhd/fpga/usrp2/top/N2x0/build-N210R4/ > u2plus.xise <- Settings/Administrator/My dependency dropped. > make[1]: *** No rule to make target `Documents/Source_code_of_uhd/fpga/usrp2/top > /N2x0/capture_ddrlvds.v', needed by `Documents/Source_code_of_uhd/fpga/usrp2/top > /N2x0/build-N210R4/u2plus.xise'. Stop. > make[1]: Leaving directory `C:/Documents and Settings/Administrator/My Documents > /Source_code_of_uhd/fpga/usrp2/top/N2x0' > make: *** [N210R4] Error 2 > > C:\Documents and Settings\Administrator\My Documents\Source_code_of_uhd\fpga\usr > p2\top\N2x0> > > > > On Jul 11, 2012, at 12:20 AM, Ian Buckley wrote: > >> Derrick, >> the only portions of the USRP database that do not provide source HDL are the Xilinx IP portions...mostly RAM's and DLL's. All required source for the ZPU should be present in the git tree. >> As a general note, all production builds and Ettus FPGA development are done in the command line environment using makefiles. Thus you'll get better support from this list if you follow that methodology rather than trying to use Xilinx's GUI methodology du jour. The various Makefile.srcs list every file required to build the design(s), which in the case of the ZPU appears to be (in opencores): >> zpu/zpu_top_pkg.vhd \ >> zpu/zpu_wb_top.vhd \ >> zpu/wishbone/wishbone_pkg.vhd \ >> zpu/wishbone/zpu_system.vhd \ >> zpu/wishbone/zpu_wb_bridge.vhd \ >> zpu/core/zpu_config.vhd \ >> zpu/core/zpu_core.vhd \ >> zpu/core/zpupkg.vhd \ >> >> -Ian >> >> On Jul 10, 2012, at 11:42 PM, Derrick Ho wrote: >> >>> Hello >>> >>> I'm trying to figure out how to add new vhdl or verilog modules to the usrp >>> so as a start I placed all the relevant files in a xilinx project. >>> In the source code I traveled to the N2x0 folder since it looked like the one that >>> matched my model. The first problem I saw was that xilinx showed an orange question >>> mark next to modules that were inside the top level unit (i.e. u2plus.v). Usually that means >>> the project doesn't know where the files are. So I went ahead and added >>> all the files from the source. >>> >>> Most of the question marks disappeared except for one. it was called "trace". >>> The file "/fpga/usrp2/opencores/zpu/core/zpu_core.vhd" seems to be the only one using it. >>> >>> The port map looks like this >>> >>> ----start snippit >>> >>> if Generate_Trace generate >>> trace_file: trace port map ( >>> clk => clk, >>> begin_inst => begin_inst, >>> pc => trace_pc, >>> opcode => trace_opcode, >>> sp => trace_sp, >>> memA => trace_topOfStack, >>> memB => trace_topOfStackB, >>> busy => busy, >>> intsp => (others => 'U') >>> ); >>> end generate; >>> >>> ----end snippit >>> >>> At first it looked like there was no component declaration, but I found it in "zpupkg.vhd" >>> >>> ---start snippit >>> >>> component trace is >>> port( >>> clk : in std_logic; >>> begin_inst : in std_logic; >>> pc : in std_logic_vector(maxAddrBitIncIO downto 0); >>> opcode : in std_logic_vector(7 downto 0); >>> sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit); >>> memA : in std_logic_vector(wordSize-1 downto 0); >>> memB : in std_logic_vector(wordSize-1 downto 0); >>> busy : in std_logic; >>> intSp : in std_logic_vector(stack_bits-1 downto 0) >>> ); >>> end component; >>> >>> ---end snippit >>> >>> >>> The only problem is that the entity that describes this component is missing. I can't seem to find it. >>> My guess is that it is an IP core. >>> >>> >>> >>> Where can I FIND or GET this component? >>> >>> >>> Derrick Ho >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >