10MHz to 32MHz?
Hi All,
another method that avoids PLL and other sources of phase noise is to
divide down to 2MHz, get a square wave signal,
low pass it to make a rough sine wave, feed it into a full wave
rectifier, (pair of diodes) and the fundamental is eliminated and
only even harmonics are left.
Lowpass to make rough sine wave of 4 MHz and repeat three more times.
The full wave rectifier provides a MOD function of the sinewave,
which has a DC offset and harmonics 2, 4, 6 etc.
This may be a low phase noise way of converting the frequencies.
Cheers, Neville Michie
Neville Michie wrote:
Hi All,
another method that avoids PLL and other sources of phase noise is to
divide down to 2MHz, get a square wave signal,
low pass it to make a rough sine wave, feed it into a full wave
rectifier, (pair of diodes) and the fundamental is eliminated and
only even harmonics are left.
Lowpass to make rough sine wave of 4 MHz and repeat three more times.
The full wave rectifier provides a MOD function of the sinewave,
which has a DC offset and harmonics 2, 4, 6 etc.
This may be a low phase noise way of converting the frequencies.
Cheers, Neville Michie
Neville
The phase noise performance will still be limited by the performance of
the divider (unless a regenerative divider is used -however these are
relatively complex, and accurate alignment is required for low phase
noise performance).
As such the phase noise performance will be no better than that obtained
by extracting the desired harmonic from the divider output.
Obtaining a low noise 50% duty cycle square wave by dividing 10MHz by 5
isn't possible.
However a 40% duty cycle reduces the fundamental (2MHz) only slightly.
One doubler could be eliminated by filtering out the second harmonic,
however an easily achievable 20% duty cycle would be better.
Diode doublers usually require an amplifier to get achieve sufficient
output, if a pair of JFETS are used as a double instead of the diodes
then an amplifier isn't required.
Bruce
From: "Lester Veenstra M0YCM K1YCM" M0YCM@veenstras.com
Subject: Re: [time-nuts] 10MHz to 32MHz?
Date: Sun, 22 Apr 2007 21:11:24 +0100
Message-ID: BEEGJPDMADIAOODLJFLPKEIOCAAA.M0YCM@veenstras.com
And if the 32 mhz source is a sealed unit, I suspect you will find that once
you mechanically set it as close as practical, that varying the Vcc will
allow you to use it as a narrow VCO.
You could induce a sub-tone directly to the VCC pin of the oscillator as well!
:P
Cheers,
Magnus
Good day,
*********** REPLY SEPARATOR ***********
On 22-Apr-07 at 21:11 Lester Veenstra M0YCM K1YCM wrote:
And if the 32 mhz source is a sealed unit, I suspect you will find that
once
you mechanically set it as close as practical, that varying the Vcc will
allow you to use it as a narrow VCO.
Fair enough. However, I need some clarification. Magnus used some terms that are utterly unfamiliar to me. See below.
<snippety>
The most straight-forward fashion is naturally to lock it through a PLL.
Highest common comparator frequency is 2 MHz, so divide 10 MHz by 5 and 32
by
16, compare with SR-gate, use either a passive lag or better yeat, and
active loop. Three digital ICs and an op-amp. If the 32 MHz reference is a crystal
then hooking into the caps for a varicap is easy enought for most hams.
I suspect a full-blown design engineer would have no trouble following this, Magnus, and I thank you for your post, but I'm afraid you lost me on a couple of things.
What is meant by 'passive lag?'
Likewise: 'active loop?'
On the IC's: I can guess at two of the digital side (divide-by-5 and divide-by-16 counters), but what would the third one be?
The op-amp I can guess at -- probably high frequency/high slew rate, I'm thinking something in the LF series. And I'm also guessing that it would be used to compare the two divided-down signals, and produce a difference voltage if they're out of phase?
The part about "hooking into the caps for a varicap" means nothing to me in its current form. Are you trying to say I'd need a varactor effect for the 32MHz source? (That's the only idea that makes sense to me).
Thanks much.
-=-=-=-=-=-=-=-=-=-=-=-
Bruce Lane, Owner & Head Hardware Heavy,
Blue Feather Technologies -- http://www.bluefeathertech.com
kyrrin (at) bluefeathertech do/t c=o=m
"If Salvador Dali had owned a computer, would it have been equipped with surreal ports?"
From: "Bruce Lane" kyrrin@bluefeathertech.com
Subject: Re: [time-nuts] 10MHz to 32MHz?
Date: Sun, 22 Apr 2007 09:05:46 -0700
Message-ID: 200704220905460850.45BD3255@192.168.42.129
Good day,
*********** REPLY SEPARATOR ***********
On 22-Apr-07 at 21:11 Lester Veenstra M0YCM K1YCM wrote:
And if the 32 mhz source is a sealed unit, I suspect you will find that
once
you mechanically set it as close as practical, that varying the Vcc will
allow you to use it as a narrow VCO.
Fair enough. However, I need some clarification. Magnus used some terms that are utterly unfamiliar to me. See below.
<snippety>
The most straight-forward fashion is naturally to lock it through a PLL.
Highest common comparator frequency is 2 MHz, so divide 10 MHz by 5 and 32
by
16, compare with SR-gate, use either a passive lag or better yeat, and
active loop. Three digital ICs and an op-amp. If the 32 MHz reference is a crystal
then hooking into the caps for a varicap is easy enought for most hams.
I suspect a full-blown design engineer would have no trouble following this, Magnus, and I thank you for your post, but I'm afraid you lost me on a couple of things.
What is meant by 'passive lag?'
That is PLLish slang for a standard RC lowpass filter.
Likewise: 'active loop?'
That is PLLish slang for an integrating loop in which you have an op-amp based
integrator, such that you have a capacitor in the negative feedback path of an
op-amp and feed the phase comparator output to the negative input through a
resistor. This is equalent to the integrator term which Bruce was refering to,
it can also be referred to as the DC path since it is is almost quiet.
You also want to balance this to control the damping, which you do by bypassing
it with a resistive path and add the result of them both, but this can be
acheived by inserting a resistor in series with the capacitor. This way you end
up having a loop filer setup which is built from two resistors, a capacitor and
an op-amp. You want a low-leakage, high impedance op-amp, so try something a
thad better than the 741...
On the IC's: I can guess at two of the digital side (divide-by-5 and divide-by-16 counters), but what would the third one be?
While there are many good phase detectors, such as the AD9901, you can get by
using a 'HC00 (or better) wired up as a secured SR-flip-flop.
Ref -> pin 13
Osc -> pin 1
pin 11 -> pin 10
pin 3 -> pin 4
pin 6 -> pin 12
pin 6 -> pin 9
pin 8 -> pin 2
pin 8 -> pin 5
pin 6 -> active loop filter (inverted output)
pin 8 -> passive loop filter (non-inverted output)
It is a quick-hack but can be made to work. The high comparator frequency of
2 MHz is to your advantage for such a quick-hack.
The drawback of the passive loop filter (RC lowpass) is that as you lower the
filter cutoff, you lower the capture & track range, which is not very good.
It is however fairly simple to get it to work.
With an active loop filter you need to be a bit more careful in how you set
your parameters.
The op-amp I can guess at -- probably high frequency/high slew rate, I'm thinking something in the LF series. And I'm also guessing that it would be used to compare the two divided-down signals, and produce a difference voltage if they're out of phase?
The phase comparator does that, the op-amp is there for filtering and mostly
LF signal works actually.
The part about "hooking into the caps for a varicap" means nothing to me in its current form. Are you trying to say I'd need a varactor effect for the 32MHz source? (That's the only idea that makes sense to me).
Yes, unless you already have a CV control, in which case it is just a matter of
hooking up.
I think you can have use for a low-tech solution like this to start with, just
to get your toes wet. After that there is an endless path to perfection!
Cheers,
Magnus
I thought about suggesting a PLL, since a couple of 74HC counters and a
74HCT4046 could do the job for less than $20 in parts. But I think a
separate VCO would be needed. It doesn't seem safe to assume that the rig's
crystal oscillator either has a varactor, or is sufficiently steerable via
its Vcc line.
The other problem is that unless you have near-superhuman analysis skills,
your PLL will NOT work optimally without actually measuring and tweaking it,
or at least modelling it in a good simulator. I don't know of any freeware
simulators for the '4046 or any other PLL chips that can be used without a
microcontroller. You could use a microcontroller and a newer chip like the
ADF4002, which is a truly-excellent part... but in my experience, even the
nicer packages like ADISimPLL deviate from reality when the VCO gain doesn't
fall within a fairly-narrow range of popular values. (I suspect they have a
bug, actually, but haven't had time to prove or disprove it.)
And of course, if you're going to use a microcontroller to run your PLL
chip, you might as well use a DDS. Honestly, I'd just rig up some dividers
and mixers, borrow some time on an SA to tune it all up, and call it a day.
-- john, KE5FX
Good day,
*********** REPLY SEPARATOR ***********
On 22-Apr-07 at 21:11 Lester Veenstra M0YCM K1YCM wrote:
And if the 32 mhz source is a sealed unit, I suspect you will find that
once
you mechanically set it as close as practical, that varying the Vcc will
allow you to use it as a narrow VCO.
And if the 32 mhz source is a sealed unit, I suspect you will find that once
you mechanically set it as close as practical, that varying the Vcc will
allow you to use it as a narrow VCO.
Full Name: Lester B Veenstra
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-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com]On
Behalf Of Magnus Danielson
Sent: Saturday, April 21, 2007 7:55 PM
To: time-nuts@febo.com; kyrrin@bluefeathertech.com
Subject: Re: [time-nuts] 10MHz to 32MHz?
From: "Bruce Lane" kyrrin@bluefeathertech.com
Subject: [time-nuts] 10MHz to 32MHz?
Date: Sat, 21 Apr 2007 11:26:23 -0700
Message-ID: 200704211126230290.4117897A@192.168.42.129
Fellow time-clockers,
I have an interesting (if a bit annoying) situation. I would like to
use one of my existing GPS standards to improve stability on one of my HF
transceivers. The problem is that said transceiver, for reasons unknown to
me, uses a 32MHz reference oscillator.
The highest GPS-lock frequency I have available is 10MHz.
Suggestions for using this to produce a 32MHz reference would be welcome, as
my skills for this kind of design are a bit rusty.
The most straight-forward fashion is naturally to lock it through a PLL.
Highest common comparator frequency is 2 MHz, so divide 10 MHz by 5 and 32
by
16, compare with SR-gate, use either a passive lag or better yeat, and
active
loop. Three digital ICs and an op-amp. If the 32 MHz reference is a crystal
then hooking into the caps for a varicap is easy enought for most hams.
Cheers,
Magnus
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