Hi All, There is issue with GPSDO when PCIe connection is used on USRP X310. On each start of any UHD based program GPSDO gets reset/power cycle. Just after starting any program that streams/receives samples GPSDO sends through UART following text: **************************************************************Firmware: rev 0.929b , built: Nov 6 2018 14:03:58 and UHD prints warning message: [WARNING] [GPS] update_cache: Malformed GPSDO string: LC_XO, Firmware Rev 0.929b This issue makes internal GPSDO in X310 useless when PCIe connection is used as it loses gps lock. When using Ethernet there's no such issue. I think it's because that for PCIe FPGA binary is reloaded on each UHD based application start. During programing FPGA lines change state, among them probably GPSDO_PWR_ENA line, what causes GPSDO power to go down for a moment. Is it possible to avoid reloading FPGA code when PCIe is used, without changing UHD source? -- Best Regards, Piotr Krysik