Von:    Stephen Farthing squirrox@gmail.com
Betreff: [time-nuts] what is the best way to multiply a 10 Mhz signal?

I did 5 MHz * 7 = 35 which is about the same, with CMOS gates and
filtering. ( in the style propagated by Wenzel)  This took a lot of filtering
to get rid of the last spurii. Too much ado.

I recommend  a 70 MHz VCXO and locking this to the 10 MHz source.

regrds, Gerhard

I'm certainly not the expert but can't you place a divide by 7 counter
in the  feedback loop of a phase lock loop.  There is a fast version
of the 4046  PPL chip that does 100Mhz and a divide by 7 is easy to
rig with TTL.

On Tue, Dec 21, 2010 at 8:35 AM, Stephen Farthing squirrox@gmail.com wrote:

--

Chris Albertson
Redondo Beach, California

On 21/12/10 16:35, Stephen Farthing wrote:

What is the application? What will the DDS output frequency be?

Maybe you could use a 70MHz (or whatever frequency you need)
VCO as the DDS clock and use the DDS as a programmable divider
to produce a 10MHz output. This could be phase locked to the
10MHz output from the LPRO-101.

--
Linux 2.6.35

I used to be in the synthesizer business (Zeta Labs)
in a previous life.  I learned to ask the customers:
what you are trying to accomplish as the end goal,
before tackling a messy problem like multiplying by
7.  Maybe you don't need to multiply by 7, but we
can't tell from your question.

Rick Karlquist N6RK

On 12/21/2010 8:35 AM, Stephen Farthing wrote:

Hi Rich....

Thanks for the reply....I have an AD9834 DDS chip I want to use for a
Frequency generator with an accuracy of 1 Hz from 0-30 Mhz. . This part can
be clocked at 75 Mhz - but unlike other DDS chips seems to have no internal
clock multipliers. So it seems to me if I can some how generate a 70 Mhz
clock signal from my rubidium standard I can solve the problem.

73s Steve

On 21 December 2010 17:36, Richard (Rick) Karlquist
richard@karlquist.comwrote:

--
It is vain to do with more that which can be done with less.

Interesting. When I used to use and build DDSs back in the early 70's, we
typically used 2.56 times the maximum required frequency for a clock, to get
above Nyquist and allow adequate filtering stop-band rejection. At the time
we could not go much higher due to limitations in device speeds, especially
the D/A. Today you can easily use a much higher clock frequency which would
simplify filtering and reduce gain variations. At 70 MHz clock you are only
at 2.333 Nyquist. Even at 2.56 by the time you get to your desired goal of
30 MHz, you will have what looks just about like a square wave. So,
filtering will be a must, and, after filtering, you will find that your
amplitude output will greatly decrease with frequency. The other question is
phase noise objectives. If that is not a real concern, then as suggested,
maybe a simple locked VCO would be the way to go. 73 - Mike

Mike B. Feher, EOZ Inc.
89 Arnold Blvd.
Howell, NJ, 07731
732-886-5960 office
908-902-3831 cell

-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Stephen Farthing
Sent: Tuesday, December 21, 2010 12:57 PM
To: Richard (Rick) Karlquist; time-nuts@febo.com
Subject: Re: [time-nuts] what is the best way to multiply a 10 Mhz signal?

Hi Rich....

Thanks for the reply....I have an AD9834 DDS chip I want to use for a
Frequency generator with an accuracy of 1 Hz from 0-30 Mhz. . This part can
be clocked at 75 Mhz - but unlike other DDS chips seems to have no internal
clock multipliers. So it seems to me if I can some how generate a 70 Mhz
clock signal from my rubidium standard I can solve the problem.

73s Steve

On 21 December 2010 17:36, Richard (Rick) Karlquist
richard@karlquist.comwrote:

--
It is vain to do with more that which can be done with less.

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This might explain a way to do it
http://physics.eou.edu/courses/phys345/lab14_pll.pdf

What this is doing is simple.  It is a 70Mhz voltage controlled oscillator
who's frequency is controlled such that every 7th cycle the phase matches
your 10MHz reference.  The example above does divide by 10 or 128 but
7 is the same thing.

The way to make a divide by 7 is to have a counter feed a comparator and
on match the comparator resets the counter.  The reset signal is your output.
It requires two 50 cent chips

Can you use 80Mhz or 100Mhz.  Either of these is easier and uses one less
chip.

On Tue, Dec 21, 2010 at 9:57 AM, Stephen Farthing squirrox@gmail.com wrote:

--

Chris Albertson
Redondo Beach, California

You may want to check out the 10MHz locked 1GHz clock I did
(using ADF4107 and a 1GHz Crystek CVCO)
http://www.qslnet.de/member/on4iy/1gclock/xlock-1g.html
and associated DDS to generate oddbal frequencies.
http://www.qslnet.de/member/on4iy/9912.html

Includes some PN measurements.

Xtof.

On 21/12/10 19:18, Mike Feher wrote:

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