Please keep this thread on the usrp-users list. The supported method for loading custom bitstreams on the n310 is to copy the .bin version of the bitstream to /lib/firmware on the SD card, which uses fpga_manager under the hood. The Ettus design flow does not use the Xilinx SDK and the N310 is not intended to be used without an operating system on the Zynq, so you're unlikely to get any support for this particular approach on this list. On Mon, Oct 21, 2019 at 7:18 AM Samuel Berhanu <samberhanu@gmail.com> wrote: > Have you been able to load a bit file, and load debug cores on the N310? > what were the steps you took to do so (I am guessing if you did, it was > through the FPGA manager?). Currently, I am having difficulty as the device > resets right after the moment a JTAG connection is used to reprogram the > PL. My colleague came up with the suggestion to not let the kernel load so > he suggested we move the fit-image-4.12 file in /primarly/boot to let > u-boot hang to be able to access the JTAG chain directly without the device > resetting on us. That way, we have been able to load and configure the PS > and PL side. > > The version I am using is 2017.4. I was able to create the project with > GUI=1 with 2017.4. The problem I am having now relates to the main I2C bus > (TCA9548, sheet 7 of the MB schematic) . > > I actually had success with getting an ACK from this bus expander with a > very simple design. What I had success with: -- a PS7 *configured preset > as ZC706,* *but changed all the MIO pin assignments and clocks according > to the Ettus HG* design configuration > > . With the modification mentioned, I was able to get the NETCLK, FPGA > device clocks and the SYSREF clocks to arrive in the FPGA. > > But using the same successful no-OS software (with a corresponding BSP > that is generated from the Ettus design hdf), when i try to interract with > the Ettus design from Xilinx SDK, the software driver reports back that > there was NOACK from TCA9548 device. > > I am a bit baffled but the only difference in PS7 configuration between > the simple design that worked and the Ettus design is the preset that I > used for the working design. Ettus' design does not apply any presets. I am > not sure but that's just my initial guess. > Any thoughts or comments are appreciated > > In the meantime, the email that I got from Ettus about a two months ago > was that the schematic should be the correct version (which I know and you > already know this) but that is not the case because for the working design > that I had there is no way if I used the schematic's MIO pin assignment i > would be able to see the clocks in the FPGA. > I am in the process of relaying this to Ettus so will relay whatever I get > back from them. > > On Fri, Oct 18, 2019 at 11:59 AM Robin Coxe <coxe@quanttux.com> wrote: > >> What version of Vivado are you using? >> For some reason, the manual on the Ettus website is for UHD version >> 3.15.0.0-69-gc350eb5a6, which requires 2018.3 and is not actually an >> official release. >> If memory serves, the actual tagged release (v.3.14.1.1) requires Vivado >> 2017.4. >> >> I've definitely created Vivado projects for the N310 with GUI=1...with >> Vivado 2017.4. Also, I don't think the schematic is actually correct, for >> the record. >> >> -Robin >> >> On Fri, Oct 18, 2019 at 8:33 AM Samuel Berhanu via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> https://www.xilinx.com/support/answers/68238.html. This pretty much is >>> the issue. >>> >>> >>> On Fri, Oct 18, 2019 at 11:13 AM Samuel Berhanu <samberhanu@gmail.com> >>> wrote: >>> >>>> Having difficulty creating a project to actually test out the N310 HG >>>> design. (I am having problems with a no-Os setup that I am trying to >>>> execute to find out what exactly the pin assignment should be for the MIOs. >>>> On a side note, the issue specifically is wrt I2C0, USB and TPM pin >>>> assignments. Schematics vs PS7 design does not seem to match up. Ettus >>>> support email from about a month ago stated schematic is right but now I am >>>> having second thoughts about it) >>>> >>>> Usually, when working with ettus products, I generate, using ettus' >>>> script with GUI=1, a project, which afterwards I save to make a tcl >>>> script for a project to impl and resynthesize it as my own project. >>>> >>>> Through this process, (mind you i have not gotten to regenerating a tcl >>>> script yet) (and this was a relatively easy fix), the custom packaged ips >>>> were not found and I had to insert them from (vivado_ipi) folder. >>>> >>>> Design went through synthesis fine. At implementation, though, I am >>>> seeing this error: >>>> (sub-design 'n310_ps_bd.bd is not generated for Synthesis target. >>>> Please open this sub-design and generate with synth_checkpoint_mode as >>>> signular in original project before adding it to current project' >>>> >>>> [image: Selection_062.bmp] >>>> >>>> I have made sure to get the ip report status, all ips are not locked. >>>> >>>> I have tried to search for answers online but nothing seems to pop up. >>>> Anyone has encountered this problem? >>>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>