High rate, high precision/accuracy time interval counter methods
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
On 5/3/2016 5:31 AM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Hi Attila,
On 05/03/2016 02:31 PM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
Getting to those rates will be challenging, especially with the LC tank.
For the higher rates a more traditional interpolator needs to be used,
charge a cap with the error pulse and sample that.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
13.3 MHz (or every 75 ns) is achievable with the HP5372A, but it had
relatively meager single-shot resolution, 200 ps, compared to its
predecessor. It uses the delay vernier approach rather than the
triggered oscillator vernier (HP5370A/B) just because of sample-rate.
The HP5371A/5372A is made to analyze jitter rather than high resolution
long term stuff. Even as the limit shifts over time, high speed will end
up having somewhat lower resolution than a lower rate could offer.
However, with higher rate, you can use the least-square methods of mine
to get results and fight the white noise that way.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Well, if you sample at sufficiently high rate, you can estimate the
rising/falling edge using least-square methods and then interpolate the
position. There is only a relatively small burst of samples needed, and
the least-square processing can be done using high-speed FPGA methods
similar to what is found in the article I sent you.
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system. The phase values can be produced at very high rates
there and the noise of such setups can be maintained relatively low
compared to the comparator systems. For such systems the noise per
phase-sample is maybe even better understood as the averaging time over
the phase vs. noise is relatively simple process to understand.
Pipeline CORDIC can be used for arctan processing.
Cheers,
Magnus
Wouldn't this be a natural application of a centroid or transition
midpoint timing TDC implemented with a pulse shaper, fast ADC, and
FPGA?
What about sampling inphase and quadrature sine waves? This should be
more amendable to a microcontroller only solution and if I had to
start working on something immediately, this is what I would try
first.
I assume in the earlier discussion Bruce mentioned these methods since
they are included on his page of the various ways to implement TDCs:
http://www.ko4bb.com/~bruce/TDC.html
On Tue, 3 May 2016 08:40:53 -0700, you wrote:
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
Rick,
Unless you uses the high-speed SERDES blocks, the jitter and systematic
noises inside FGPAs can be pretty prohibitive.
Enrico Rubiola and his team have made some of the best characterizations
of FPGAs I've seen, but I know from several other experinces that timing
can uhm shift around.
I proposed some 10 years ago to use the 10 Gb/s SERDES for 100 ps
resolution counter, the chip that could support it then could do 8
channels. It had some fancy tweaking so you could fine-tune the sampling
point to align channels up. Would still be a fun project to do.
The normal logic path isn't "as fun".
I'd say that the precision timing stuff should be done in a separate
front-end, but the sea of logic to handle all the dataflows can be done
in a FPGA.
Cheers,
Magnus
On 05/03/2016 05:40 PM, Richard (Rick) Karlquist wrote:
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
On 5/3/2016 5:31 AM, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build
one...yet :-)
Attila Kinali
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
I&Q sine sampling works, but a continuous sampling allows for N samples
to reduce the noise by sqrt(N) rather than 2 samples. The white-noise
will be the limiting factor for the higher rates.
Least-square estimation provides a 2.5 dB improvement over straight
sample average.
Cheers,
Magnus
On 05/03/2016 10:33 PM, David wrote:
Wouldn't this be a natural application of a centroid or transition
midpoint timing TDC implemented with a pulse shaper, fast ADC, and
FPGA?
What about sampling inphase and quadrature sine waves? This should be
more amendable to a microcontroller only solution and if I had to
start working on something immediately, this is what I would try
first.
I assume in the earlier discussion Bruce mentioned these methods since
they are included on his page of the various ways to implement TDCs:
http://www.ko4bb.com/~bruce/TDC.html
On Tue, 3 May 2016 08:40:53 -0700, you wrote:
HP/Agilent/Keysight laser interferometers
measure at the kind of rates you are talking
about and (last time I heard) could divide
an interference fringe down to 1/512 of a
wavelength. As you say, they definitely use
an ASIC with a ring oscillator. Perhaps
there is some way you could repurpose the
interferometer electronics to make your
measurement.
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Rick
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Massive parallelism of a simple NUTT style interpolator (charge capacitor with
say 10mA, rundown with say 1uA, use 100MHz clock or faster clock ).
With a custom IC for the analog part, a resolution of 1ps should be feasible.
An FPGA can do all the non critical stuff like the rundown counting.
The problem is to ensure that the front end logic that selects the next non-
busy interpolator doesn't accumulate excessive jitter from cascaded gates.
The same issue of accumulated jitter produced by cascaded gates/inverters can
limit the performance of vernier delay line style interpolators. Minimising
the number of series inverters by using a higher frequency clock (100MHZ,
1GHz??) should help somewhat.
Bruce
On Tue, 3 May 2016 08:40:53 -0700
"Richard (Rick) Karlquist" richard@karlquist.com wrote:
You also might consider that over 25 years
ago, HP developed the 5313X counters with
interpolators implemented in FPGA's. The
FPGA's available now are vastly more
sophisticated and much faster. Perhaps there
is a way you do your ASIC in an FPGA.
The limit for TDCs in FPGAs seems to be around 5-20ps RMS
(which makes it more like 15-50ps in "real" precision)
depending on type and technology. Going down to below 20ps
usually means to take the latest tech FPGA with lots of
redundant structures, which makes the whole thing quite expensive.
If you really do need an ASIC, the best way
to get that done is to partner with a university
and have some PhD student design it. Universities
often have arrangements to do this.
Yes. That's one approach. And actually, we are currently going
that way for one of the projects I am doing. The problem with this
is that it's not exactly cheap (you need 10k at least to do anything)
and that any commercial use (like selling the chips to someone else
unless it's an academic institute again) is strictly prohibited.
Not to mention very limited availability (you get 40 pieces and that's it)
I was looking for something that can be produced more generally.
Possibly even by a dedicated hobbyist.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system.
The "signal" is not a sinusoid, but discrete events. Think of it
as incomming pulses and you want to measure their arrival time.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
Integrating A Time interval to charge TAC at the front end of a capacitive charge redistribution SAR ADC should allow a conversion time of 300ns or so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate without too many cascaded gates in the selection logic for the next available TAC.
Bruce
On Wednesday, 4 May 2016 12:00 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Massive parallelism of a simple NUTT style interpolator (charge capacitor with
say 10mA, rundown with say 1uA, use 100MHz clock or faster clock ).
With a custom IC for the analog part, a resolution of 1ps should be feasible.
An FPGA can do all the non critical stuff like the rundown counting.
The problem is to ensure that the front end logic that selects the next non-
busy interpolator doesn't accumulate excessive jitter from cascaded gates.
The same issue of accumulated jitter produced by cascaded gates/inverters can
limit the performance of vernier delay line style interpolators. Minimising
the number of series inverters by using a higher frequency clock (100MHZ,
1GHz??) should help somewhat.
Bruce
time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.
One method is to have the event trigger sampling of a pair of quadrature phase sinewaves. eg LT1407A-1 dual 14 bit SAR ADC can sample a quadrature pair of 10MHz sine waves with ~ 5ps resolution in the computed phase.
Bruce
On Wednesday, 4 May 2016 10:00 PM, Attila Kinali <attila@kinali.ch> wrote:
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system.
The "signal" is not a sinusoid, but discrete events. Think of it
as incomming pulses and you want to measure their arrival time.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On 05/04/2016 10:38 AM, Attila Kinali wrote:
On Tue, 3 May 2016 22:31:14 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
An alternative to the edge estimator method is to continuously sample,
mix with a reference frequency, decimate and then do arc-tangent of the
I/Q samples. This is what is used for phase-noise measurement such as
the Symmetricom/Microsemi test-kits, TimePod, and also the new R&S
phase-noise system.
The "signal" is not a sinusoid, but discrete events. Think of it
as incomming pulses and you want to measure their arrival time.
Which cuts away that option, yes. Naturally. The mixdown variant assumes
a repeating pulse patter, but it does not assume sine.
Cheers,
Magnus
Am 04.05.2016 um 10:46 schrieb Bruce Griffiths:
Integrating A Time interval to charge TAC at the front end of a capacitive charge redistribution SAR ADC should allow a conversion time of 300ns or so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate without too many cascaded gates in the selection logic for the next available TAC.
Bruce
One or two years ago I investigated a solution around a 16 Bit / 100
MSPS ADC (LTC2165), a 2C64 Coolrunner,
an Avago PHEMT as current switch and a little bit of analog voodoo. That
would have fit on a 2"*2" board.
Good enough for a 10 MHz event rate, with some easy pipelining for at
least 20 MHz.
That includes the coarse counter from the last 1pps.
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
regards, Gerhard
Hi,
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
Cheers,
Magnus
On 05/04/2016 10:46 AM, Bruce Griffiths wrote:
Integrating A Time interval to charge TAC at the front end of a capacitive charge redistribution SAR ADC should allow a conversion time of 300ns or so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz timestamp rate without too many cascaded gates in the selection logic for the next available TAC.
Bruce
On Wednesday, 4 May 2016 12:00 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
On Tuesday, May 03, 2016 02:31:17 PM Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
Massive parallelism of a simple NUTT style interpolator (charge capacitor with
say 10mA, rundown with say 1uA, use 100MHz clock or faster clock ).
With a custom IC for the analog part, a resolution of 1ps should be feasible.
An FPGA can do all the non critical stuff like the rundown counting.
The problem is to ensure that the front end logic that selects the next non-
busy interpolator doesn't accumulate excessive jitter from cascaded gates.
The same issue of accumulated jitter produced by cascaded gates/inverters can
limit the performance of vernier delay line style interpolators. Minimising
the number of series inverters by using a higher frequency clock (100MHZ,
1GHz??) should help somewhat.
Bruce
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time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.
For the sensor timestamping you can try replicate an avalanche effect
with a device which uses a pn-pn substrate configuration ... or
something similar to the avalanche photodiodes.
The avalanche photodiode has very high gain and a response time of some
ps (5ps a commercial APD).
This system may cause some effects like high noise and would need high
breakdown voltages however.
The spurious capacitances can be minimized because in APDs it depends on
the sensor area, which is not needed in your case.
Regards,
Ilia.
On 05/03/16 12:31, Attila Kinali wrote:
Hi,
We had here a discussion about measuring events (ie time stamping
them precisely) with high rates. As some of you know, Javier and
his group, Bruce and me are working on a system that should give
us something better than 10ps (my guess is that we should get close
to 1ps) at a rate of (guestimated) 1MHz per channel. (Based on the
excitation of a LC tank and measuring the ring-down/phase with an ADC).
As it is with researches, we want the moon, and prossible even more.
So we were talking about getting the measurement rate up even higher,
to 10MHz and if possible 50MHz with the same precision. The above
approche will not work above 1MHz. Using different filters it might
be possible to get it up to maybe 10MHz, but it would be an awkward
design at best.
The only methods I am aware of (and could find) that achieve such high
rates are those, based on (vernier) delay lines (and their equivalent
ring oscillator ones) in ASICs. But this means that a costly ASIC needs
to be produced.
Does someone know of other methods that could achieve high measurements
rates with better than 10ps precision/accuracy? (This question is mostly
a hypothetical question out of interest, I don't plan to build one...yet :-)
Attila Kinali
--
Ilia Platone
via Ferrara 54
47841
Cattolica (RN), Italy
Cell +39 349 1075999
On Wednesday, May 04, 2016 02:22:22 PM Gerhard Hoffmann wrote:
Am 04.05.2016 um 10:46 schrieb Bruce Griffiths:
Integrating A Time interval to charge TAC at the front end of a capacitive
charge redistribution SAR ADC should allow a conversion time of 300ns or
so.. Using 16 such TDCs should permit 1ps resolution with a 50MHz
timestamp rate without too many cascaded gates in the selection logic for
the next available TAC. Bruce
One or two years ago I investigated a solution around a 16 Bit / 100
MSPS ADC (LTC2165), a 2C64 Coolrunner,
an Avago PHEMT as current switch and a little bit of analog voodoo. That
would have fit on a 2"*2" board.
Good enough for a 10 MHz event rate, with some easy pipelining for at
least 20 MHz.
That includes the coarse counter from the last 1pps.
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
regards, Gerhard
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the
instructions there.
Yes, taking advantage of the fact that one merely uses the fine time interval
measurement to measure the delay of a synchroniser clocked with the same clock
as the ADC makes the design relatively simple. The output of the synchroniser
samples a counter clocked with the same clock as the ADC to produce the fine
count. The Time to amplitude converter output is merely held for 1 or 2 clock
cycles so the ADC can sample the relevant part of the output. The TAC output
is then reset to zero (or better the opposite limit of the ADC input). Either
a buffer is used between the TAC and ADC or a direct connection should be
feasible as long as the effect of sampling during ramping of the TaC output
(TAC output capacitor is being charged) is corrected for. That is correcting
for the charge transfer during this undesired sample. The sample taken when
the TAC is in hold being corrected for the charge transfer incurred by the
sample taken during ramping. Alternatively the TAC current could be used to
drrive a network with a suitable impulse response so that no explicit reset is
required. The output of this network being sampled by the ADC. The fine time
interval can then be recovered by curve fitting to the samples taken by the
ADC.
Bruce
Am 05.05.2016 um 01:55 schrieb Bruce Griffiths:
On Wednesday, May 04, 2016 02:22:22 PM Gerhard Hoffmann wrote:
But we stayed with a classical time stretcher, and my private project
pipeline is already full.
Talking about my own pipeline:
I have finally ordered today the first 20 samples of my OCXO carrier
board for
OCXOs that can be locked to an external ref, 1pps out, optional doubler
etc...
It can also be a home for Tom's picDIV.
I just imagine a gang of 16 MTI-260s, each slooowly locked to an
external ref
with their outputs wilkinsoned together to make a make a really low phase
noise 10 MHz source. I have bought a pretty number of those Lucent 24386
units without GPS for their MTis. :-) I mean, we cannot get those
BVAs anymore.
Screen dump of the Board:
http://www.hoffmann-hochfrequenz.de/downloads/ocxo_carrier_screendump.png
Sorry for the red/green blind.
regards, Gerhard
Gerhard wrote:
I just imagine a gang of 16 MTI-260s, each slooowly locked to an
external ref with their outputs wilkinsoned together to make a
make a really low phase noise 10 MHz source. I have bought a
pretty number of those Lucent 24386 units without GPS for their
MTis. :-) I mean, we cannot get those BVAs anymore.
regards, Gerhard
I have been thinking along the same lines, to combine multiple OCXOS's to
obtain lower phase noise. But an N-way Wilkinson could get tedious. After
you calculate the impedances for each leg, you then have to convert them to
lumped-element equivalents to run at 10 MHz, as shown here:
http://www.microwaves101.com/encyclopedias/lumped-element-wilkinson-splitters
The contribution from each OCXO may not be perfectly balanced, and it may
be difficult to calculate the relative contribution of each, especially
when you consider component tolerances. The isolation between units can be
fairly low; perhaps -13dB to -20dB. This could have serious effects when
running into a PLL. The Wilkson is a relatively narrow-band device and
could not be used for other oscillator banks at considerably different
frequencies.
I propose using a simple resistive combiner. The loss is -6dB, which can
easily be made up in the distribution amplifier. The balance is as perfect
as the resistor tolerances you use. Depending on how you model the OCXO
output stage, the isolation can be better than -40dB from a single unit.
I am attaching LTspice files to show the loss from each oscillator to the
output, and the isolation between oscillators. I used 10 units to help a
little in mental calculations for sanity checking.
The noise contribution is determined by the resistor network. In this
example, it is 5 Ohms in parallel with 5 ohms, or 2.5 ohms. The
contribution of the combiner is then negligible. A resistive combiner is
inherently broadband, and could easily be used over a 100:1 frequency range
with a little care in construction.
I think isolation is the main deal. When you have a bank of oscillators at
the same frequency feeding a pll that is supposed to respond to only one,
the effect of the other units could be significant. It may be necessary to
further isolate the units by providing separate outputs to feed the pll and
the combiner.
But in principle, I think it is a very good idea.
Mike
Hi
Be careful of isolation specs on some of these combiners / splitters. Often they are deponent on the return loss
of the signal source. An OCXO that presets a 12 db return loss is doing ok. One that is past 20 db is doing quite well.
Bob
On May 5, 2016, at 7:00 PM, Mike Monett timenuts@binsamp.e4ward.com wrote:
Gerhard wrote:
I just imagine a gang of 16 MTI-260s, each slooowly locked to an
external ref with their outputs wilkinsoned together to make a
make a really low phase noise 10 MHz source. I have bought a
pretty number of those Lucent 24386 units without GPS for their
MTis. :-) I mean, we cannot get those BVAs anymore.
regards, Gerhard
I have been thinking along the same lines, to combine multiple OCXOS's to
obtain lower phase noise. But an N-way Wilkinson could get tedious. After
you calculate the impedances for each leg, you then have to convert them to
lumped-element equivalents to run at 10 MHz, as shown here:
http://www.microwaves101.com/encyclopedias/lumped-element-wilkinson-splitters
The contribution from each OCXO may not be perfectly balanced, and it may
be difficult to calculate the relative contribution of each, especially
when you consider component tolerances. The isolation between units can be
fairly low; perhaps -13dB to -20dB. This could have serious effects when
running into a PLL. The Wilkson is a relatively narrow-band device and
could not be used for other oscillator banks at considerably different
frequencies.
I propose using a simple resistive combiner. The loss is -6dB, which can
easily be made up in the distribution amplifier. The balance is as perfect
as the resistor tolerances you use. Depending on how you model the OCXO
output stage, the isolation can be better than -40dB from a single unit.
I am attaching LTspice files to show the loss from each oscillator to the
output, and the isolation between oscillators. I used 10 units to help a
little in mental calculations for sanity checking.
The noise contribution is determined by the resistor network. In this
example, it is 5 Ohms in parallel with 5 ohms, or 2.5 ohms. The
contribution of the combiner is then negligible. A resistive combiner is
inherently broadband, and could easily be used over a 100:1 frequency range
with a little care in construction.
I think isolation is the main deal. When you have a bank of oscillators at
the same frequency feeding a pll that is supposed to respond to only one,
the effect of the other units could be significant. It may be necessary to
further isolate the units by providing separate outputs to feed the pll and
the combiner.
But in principle, I think it is a very good idea.
Mike
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Am 06.05.2016 um 01:00 schrieb Mike Monett:
I have been thinking along the same lines, to combine multiple OCXOS's to
obtain lower phase noise. But an N-way Wilkinson could get tedious. After
you calculate the impedances for each leg, you then have to convert them to
lumped-element equivalents to run at 10 MHz, as shown here:
NoNoNo, you can build a replacement with a 1:1 balun transformer and a
100 Ohms resistor.
With a little bit of ferrite this is both broadband and small.
It presents a 25 Ohms input resistance in a 50 Ohm system, so you need
another wideband
transformer with a 2/3 windings ratio. The resulting 4/9 impedance ratio
is close enough
to provide the impedance match from 25 to the 50 Ohm source.
That's probably what's inside a MiniCircuits PSC2-1. I have never opened
one but I don't
have much doubt.
They also have solutions for 8:1 and 16:1, but it can be cheaper d.i.y..
Someone in the US is currently selling 10 PSC2-1 on ebay IIRC. But for
me being in Europe the
transport would probably cost more than what it's worth.
regards, Gerhard
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
Attila Kinali
--
Reading can seriously damage your ignorance.
-- unknown
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
You can run the ADC on constant 100 MHz for example. The charged
capacitor has to wait an
extra 0 to 10 ns until it is read out. That is easy. In a time
stretcher you must keep the charge and
discharge it in a controlled way in 50 usec, and over that time, bias
currents etc really
do play a role.
regards, Gerhard
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
Hi
On May 8, 2016, at 7:08 PM, Gerhard Hoffmann dk4xp@arcor.de wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is done,
we can simply short the capacitor in the next clock/s to prepare for the next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
… but how about the rest of us :)
Bob
regards, Gerhard
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Yes, just a synchroniser clocked with the same clock as the ADC.The interpolator measures the synchroniser delay by charging the capacitor in the interval between the occurrence of the transition to be time stamped and when the output of the synchroniser recognises this transition.The ADC samples the capacitor voltage on the next clock.In reality the ADC samples its input continuously and the relevant sample is flagged by the synchroniser and associated logic.
Buffering the capacitor voltage avoids the need to correct for the effect of sampling the capacitor voltage during runup.However the buffer isn't essential as long as the correction is made and the ADC input is essentially capacitive.The ramp capacitor should be somewhat larger than the ADC input capacitance.
Bruce
On Monday, 9 May 2016 12:01 PM, Gerhard Hoffmann <dk4xp@arcor.de> wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
....
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.
On Sun, 8 May 2016 21:53:56 +0200, you wrote:
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
Attila Kinali
An integrating time to voltage converter effectively is an external
sample and hold so pipelined analog to digital converters are not a
problem except in complexity dealing with their latency.
Huh, Flash ADCs really are almost gone now and I did not even notice.
TI still has some available.
I wonder what the fastest SAR ADCs are now. Linear Technology is up
to 18 bits and 15 Msps in the same device but if it was the only
option, then its cost would convince me to consider alternative
designs.
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
On Mon, 9 May 2016 01:08:05 +0200, you wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
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and follow the instructions there.
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David <davidwhess@gmail.com> wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
On Mon, 9 May 2016 01:08:05 +0200, you wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
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Sure, and then we are back to a transition midpoint timing TDC. Or AC
couple it for a centroid timing TDC. These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.
I was just wondering about the speed limitations of a time to
amplitude based TDC. I am more comfortable with analog design than
using FPGAs.
On Mon, 9 May 2016 03:35:46 +0000 (UTC), you wrote:
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
Hi,
On 05/08/2016 09:53 PM, Attila Kinali wrote:
On Wed, 4 May 2016 15:26:37 +0200
Magnus Danielson magnus@rubidium.dyndns.org wrote:
Indeed. ADC conversion speed is not a big issue these days, so the Nutt
style of interpolator is just expensive to parallelize for speed, the
time-to-voltage system is better and should have a much better
recycle-time and thus result in less hardware needs.
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the sampling
circuitry are basically extinct.
You can let the ADC convert as a continuous process as long as you
filter out the samples you are interested in.
Cheers,
Magnus
Hi
Simple answer:
You are likely using an NPO cap and it’s not a big deal.
Bob
On May 8, 2016, at 9:49 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
On Mon, 9 May 2016 01:08:05 +0200, you wrote:
Am 08.05.2016 um 21:53 schrieb Attila Kinali:
...
Maybe I was too short. We have control over the charging current source,
and when we switch it off, the status quo is kept. Then when the ADC is
done,
we can simply short the capacitor in the next clock/s to prepare for the
next cycle.
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
regards, Gerhard
time-nuts mailing list -- time-nuts@febo.com
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On Sun, 8 May 2016 20:04:39 -0400
Bob Camp kb8tq@n1k.org wrote:
Attilla, we could discuss that on a sunny evening in Saarbrücken in a
beer garden if you like. The season starts :-)
… but how about the rest of us :)
How about a time-nuts conference/meet-up? :-)
And yes, i'm serious.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Since the GSPS sampling ADCs all appear to use an input buffer with relatively low value resistors between the differential inputs or connected to a midpoint bias voltage, some kind of high impedance buffer is needed between the TAC capacitor and the ADC input when using such ADCs. The highest clock frequency for capacitive input pipeline ADCs appears to be about 300MHz. A 1GSPS ADC relaxes the performance requirements of the TAC significantly making it easier to achieve 1ps or less noise.The trade off is that a discrete TAC may not be fast enough due to parasitic bond wire inductances etc. All monolithic TACs with 1ps resolution have been designed using standard IC processing.
Bruce
On Tuesday, 10 May 2016 12:14 AM, David <davidwhess@gmail.com> wrote:
Sure, and then we are back to a transition midpoint timing TDC. Or AC
couple it for a centroid timing TDC. These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.
I was just wondering about the speed limitations of a time to
amplitude based TDC. I am more comfortable with analog design than
using FPGAs.
On Mon, 9 May 2016 03:35:46 +0000 (UTC), you wrote:
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
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and follow the instructions there.
In this case though we are talking about pushing the TAC resolution to
14 bits or maybe higher and that is about the level where dielectric
absorption starts to become a problem in all but the better film
capacitors. NP0 ceramics are perhaps more than an order of magnitude
worse than the best film dielectrics.
When I have built slow sample and hold circuits in the past, I did not
have a problem with dielectric absorption in NP0 capacitors however I
also did not push the resolution so far and the hold step was a larger
issue. For fast sample and hold circuits using diode bridges, the
sample capacitance is much smaller (or only parasitic) and resolution
was even lower so there was no problem there either. In slow
integrating converters, NP0 ceramics are poor at best.
15 to 50 Msps and 12+ bits is an area where I have not experimented so
I just wondered if the relatively poor dielectric absorption of NP0
would limit resolution. Testing it would be fun and low value
polyphenylene sulfide film capacitors are available as a benchmark.
I am a little dubious of getting a clean reset as well. :) This would
be one of those places where I would consider using a bipolar
transistor with the collector and emitter reversed unless a MOSFET or
closed loop reset was better.
On Mon, 9 May 2016 07:43:19 -0400, you wrote:
Hi
Simple answer:
You are likely using an NPO cap and its not a big deal.
Bob
On May 8, 2016, at 9:49 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
Its probably easier/cheaper to construct a suitable filter for a GSPS ADC than to construct a TAC that is fast enough to suit an ADC with a GHz clock. Minimising the emitter to emitter inductance of a longtailed pair or equivalent is key to achieving a fast enough switching time for a suitable TAC. The reset switch also needs to have sub nanosecond turn on and turn off. Saturated bipolar switches are too slow. The classical dual diode clamped reset switch driven by a fast switching current source should work well if the parasitic interconnect inductances can be kept low enough.A custom IC is probably the only effective solution for such a TAC. The somewhat heroic measures employed in the Wavecrest counters is perhaps the limit of discrete construction techniques.
Bruce
On Tuesday, 10 May 2016 1:08 AM, Bruce Griffiths <bruce.griffiths@xtra.co.nz> wrote:
Since the GSPS sampling ADCs all appear to use an input buffer with relatively low value resistors between the differential inputs or connected to a midpoint bias voltage, some kind of high impedance buffer is needed between the TAC capacitor and the ADC input when using such ADCs. The highest clock frequency for capacitive input pipeline ADCs appears to be about 300MHz. A 1GSPS ADC relaxes the performance requirements of the TAC significantly making it easier to achieve 1ps or less noise.The trade off is that a discrete TAC may not be fast enough due to parasitic bond wire inductances etc. All monolithic TACs with 1ps resolution have been designed using standard IC processing.
Bruce
On Tuesday, 10 May 2016 12:14 AM, David davidwhess@gmail.com wrote:
Sure, and then we are back to a transition midpoint timing TDC. Or AC
couple it for a centroid timing TDC. These require a lot more
processing to generate a result compared to a time to amplitude
converter but with economical FPGAs and ARM microcontrollers, maybe
this does not matter.
I was just wondering about the speed limitations of a time to
amplitude based TDC. I am more comfortable with analog design than
using FPGAs.
On Mon, 9 May 2016 03:35:46 +0000 (UTC), you wrote:
Another option is to use a low pass filter to increase the transition times of the signal to be timestamped and use a pipelined ADC to sample the filter output.Perhaps something like the attached filter derived from:
http://bears.ucsb.edu/rad/pubs/conference/MTT_S_2004.pdf
May be effective in that it has near Gaussian response with relatively low out of band SWR.
Bruce
On Monday, 9 May 2016 3:01 PM, David davidwhess@gmail.com wrote:
How much will dielectric absorption in the capacitor affect the
accuracy of the result with such a high conversion rate? I am used to
dealing with it on much longer time scales and higher resolutions.
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and follow the instructions there.
Hoi Bruce,
On Mon, 9 May 2016 23:34:24 +0000 (UTC)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Its probably easier/cheaper to construct a suitable filter for a GSPS ADC
than to construct a TAC that is fast enough to suit an ADC with a GHz clock.
Probably.
Minimising the emitter to emitter inductance of a longtailed pair or
equivalent is key to achieving a fast enough switching time for a suitable
TAC.
How does one minimize this inductance? The only way I am aware of is
to use a package with a pair of transistors with common emiter pin.
The somewhat heroic measures employed in the Wavecrest counters is
perhaps the limit of discrete construction techniques.
Are these heroic measures documented somewhere?
So far I have not even seen a block diagram of a Wavecrest counter,
much less a schematic.
Attila kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Hoi Attila
Yes, the only way to reduce emitter-emitter inductance is indeed to connect them on the die. Its even better if the current source transistor collector is also connected to the common emitter node of the long tailed pair on the die as this minimises the capacitance at this node.
Alternatively one can add a small series resistance to reduce the associated emitter circuit time constant as Wavecrest do.
The Wavecrest patent is somewhat detailed and complete with reasonably detailed circuit diagrams and explanatory text.
US6185509
US6194925 ***************
US6226231US4908784
Bruce
On Tuesday, 10 May 2016 9:17 PM, Attila Kinali <attila@kinali.ch> wrote:
Hoi Bruce,
On Mon, 9 May 2016 23:34:24 +0000 (UTC)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Its probably easier/cheaper to construct a suitable filter for a GSPS ADC
than to construct a TAC that is fast enough to suit an ADC with a GHz clock.
Probably.
Minimising the emitter to emitter inductance of a longtailed pair or
equivalent is key to achieving a fast enough switching time for a suitable
TAC.
How does one minimize this inductance? The only way I am aware of is
to use a package with a pair of transistors with common emiter pin.
The somewhat heroic measures employed in the Wavecrest counters is
perhaps the limit of discrete construction techniques.
Are these heroic measures documented somewhere?
So far I have not even seen a block diagram of a Wavecrest counter,
much less a schematic.
Attila kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Am 09.05.2016 um 10:08 schrieb Magnus Danielson:
Hi,
On 05/08/2016 09:53 PM, Attila Kinali wrote:
True and not true. Yes, there are many ADCs that do high conversion
rates, but these are optimized for piplined applications where
conversion
happens at a constant rate. Ie they expect a constant conversion clock
with a constant rate. If you want to trigger conversion at an
arbitrary time,
you either have to build your own sampler or need to use one of the
non-pipelined ADCs whic are much slower (IIRC they stop around 5-10Msps
aka >100ns conversion time). Flash ADCs with direct access to the
sampling
circuitry are basically extinct.
You can let the ADC convert as a continuous process as long as you
filter out the samples you are interested in.
And, at least for the LTC2165, you could really use the encode clock to
read the result
of the capacitor immediately. All one would have to do is to flush the
pipeline with
5 or 6 clocks after the encode, with a cycle time not much faster than
10 ns and
not slower than 1 usec.
That seems not too hard to do but costs a differential mux in the encode
lines.
We then would not need to switch the current source, it could degenerate
to a
20V source with a resistor & safety clamps; that would be as linear as
it gets.
The reset level could be clamped by a Sky or Avago phemt, they can
swallow the
current easily, are blinding fast and do not drop a voltage for the base
current
over Re (from Gummel-Poon model). And an inverse transistor may have less
Re, but also less beta and therefore more base current.
I have already built a time stretcher and was restricted to spaceworthy
components;
those Intersil transistor arrays had the only acceptable PNPs. These
flatpacks are
huge, and the legs are endless; anything more complicated than a simple
current mirror would oscillate or would at least lurch to its
destination, and you
cannot simply damp it to death. Not funny.
Minimizing the E-E-inductance: The next best thing to an onchip-connection
might be abusing 2 Infineon SiGETs on the 2 sides of a thin board; they
are optimized
for low emitter inductance and have 2 emitter legs each. And their Early
voltage
is huge, so they are not impressed by the VCE changes of the current source.
(SiGe BFP650, 750 etc, available in a tiny package)
regards, Gerhard