Hello everyone, I synthesized and mapped the B210 FPGA code provided in https://github.com/EttusResearch/fpga. However, there are some unwired, floating wires in the RTL schematic, I attached a screen shot of it. Another abnormality in the RTL schematic is in b200_core module. Only two of the input wires are not connected and those are rx0 and rx1 (Screen shot is attached). Are not those are the main output of the ADC? If not, where is the main output of the ADC? Looking forward your answers, Altug Kaya

Hi Altug, Have you tried tracing those nets in the Verilog source code? Jonathon On Mon, Jun 26, 2017 at 2:57 AM, altuğ kaya via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello everyone, > > I synthesized and mapped the B210 FPGA code provided in > https://github.com/EttusResearch/fpga. However, there are some unwired, > floating wires in the RTL schematic, I attached a screen shot of it. > > Another abnormality in the RTL schematic is in b200_core module. Only two > of the input wires are not connected and those are rx0 and rx1 (Screen shot > is attached). Are not those are the main output of the ADC? If not, where > is the main output of the ADC? > > Looking forward your answers, > Altug Kaya > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Dear Jonathon Pendlum, Thank you for your advice. I traced the top module in order to check if there is a floating wire or not and I realized that there is no floating or unconnected wire. The problem stems from the RTL schematic. RTL is not a reliable way to observe module connections. I switched to Technology Schematic by choosing keep_hierarchy as soft in order to observe at least some modules. Then, I select b200_io and b200_core and realized that outputs of b200_io, namely rx_i0 and rx_q0, are connected to the input of the b200_core, namely rx_0. Thank you, Altug On Mon, Jun 26, 2017 at 6:01 PM, Jonathon Pendlum < jonathon.pendlum@ettus.com> wrote: > Hi Altug, > > Have you tried tracing those nets in the Verilog source code? > > Jonathon > > On Mon, Jun 26, 2017 at 2:57 AM, altuğ kaya via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hello everyone, >> >> I synthesized and mapped the B210 FPGA code provided in >> https://github.com/EttusResearch/fpga. However, there are some unwired, >> floating wires in the RTL schematic, I attached a screen shot of it. >> >> Another abnormality in the RTL schematic is in b200_core module. Only two >> of the input wires are not connected and those are rx0 and rx1 (Screen shot >> is attached). Are not those are the main output of the ADC? If not, where >> is the main output of the ADC? >> >> Looking forward your answers, >> Altug Kaya >> >> >> >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >