RP
Robert.Poehlmann@dlr.de
Mon, Dec 9, 2019 3:31 PM
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
NT
Nate Temple
Mon, Dec 9, 2019 6:38 PM
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to
stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag
v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but
then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module
'noc_shell__parameterized9'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just
trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one
compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
(LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to
stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi all!
>
> I tried to compile the default RFNoC image for the N310, using UHD on tag
> v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
>
> Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but
> then Vivado shows the following errors:
>
> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
> 'STR_SINK_FIFOSIZE'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
> ERROR: [Synth 8-521] parameter assignment could not be resolved to a
> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
> ERROR: [Synth 8-196] conditional expression could not be resolved to a
> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
> ERROR: [Synth 8-6156] failed synthesizing module
> 'noc_shell__parameterized9'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
> ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
>
> The full build.log file is attached. I did not modify any files, just
> trying to compile the RFNoC example as provided.
>
>
>
>
> Btw I also tried to build the default image with "make N310_XG", this one
> compiles but failed later during DRC:
>
> [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
> For example, the following two ports in this bank have conflicting VCCOs:
> ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
> (LVCMOS18, requiring VCCO=1.800)
> [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
NT
Nate Temple
Mon, Dec 9, 2019 7:43 PM
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to
stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag
v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully,
but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module
'noc_shell__parameterized9'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just
trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one
compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
(LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked
below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com> wrote:
> Hi Robert,
>
> Thanks for the bug report.
>
> If you're just trying to use RFNoC at this point, I would recommend to
> stick with the latest stable release, which at this time is v3.14.1.1.
>
> Note, 3.14.x.x UHD will require Vivado 2017.4.
>
>
> Regards,
> Nate Temple
>
> On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi all!
>>
>> I tried to compile the default RFNoC image for the N310, using UHD on tag
>> v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
>>
>> Running "make N310_RFNOC_XG", the IP cores are compiled successfully,
>> but then Vivado shows the following errors:
>>
>> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
>> 'STR_SINK_FIFOSIZE'
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>> ERROR: [Synth 8-521] parameter assignment could not be resolved to a
>> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>> ERROR: [Synth 8-196] conditional expression could not be resolved to a
>> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
>> WARNING: [Synth 8-693] zero replication count - replication ignored
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
>> WARNING: [Synth 8-693] zero replication count - replication ignored
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
>> WARNING: [Synth 8-693] zero replication count - replication ignored
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
>> ERROR: [Synth 8-6156] failed synthesizing module
>> 'noc_shell__parameterized9'
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
>> ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
>> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
>> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
>> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
>> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
>>
>> The full build.log file is attached. I did not modify any files, just
>> trying to compile the RFNoC example as provided.
>>
>>
>>
>>
>> Btw I also tried to build the default image with "make N310_XG", this one
>> compiles but failed later during DRC:
>>
>> [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
>> For example, the following two ports in this bank have conflicting VCCOs:
>> ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
>> (LVCMOS18, requiring VCCO=1.800)
>> [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users@lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
RP
Robert.Poehlmann@dlr.de
Tue, Dec 10, 2019 4:46 PM
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.commailto:nate.temple@ettus.com> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
USRP-users mailing list
USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com<mailto:nate.temple@ettus.com>> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
NT
Nate Temple
Tue, Dec 10, 2019 4:57 PM
Hi Robert,
This patch/line change detailed below should resolve that issue and will be
included in the official 3.15.0.0 release:
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8k+7:8k],
set_data_bclk[32k+31:32k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
2**(STR_SINK_FIFOSIZE[8k+7:8k]+3);
2**(STR_SINK_FIFOSIZE[8k+7:8k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of
the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM Robert.Poehlmann@dlr.de wrote:
Hi Nate!
I followed the guide in
https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus
ended up with Vivado 2018.3 and then later found out this requires UHD
3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1
this would be fixed, but apparently that is not the case. Now I went back
to 2018.3 (clean re-install) and installed the patch AR#71898. The standard
N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and
split_stream, specifically). Leaving these out, the RFNoC image does
compile. Not sure what exactly is the problem, though. The recent commit
https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked
below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple nate.temple@ettus.com wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to
stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag
v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but
then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module
'noc_shell__parameterized9'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just
trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one
compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
(LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Robert,
This patch/line change detailed below should resolve that issue and will be
included in the official 3.15.0.0 release:
---
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8*k+7:8*k],
set_data_bclk[32*k+31:32*k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
- localparam [31:0] STR_SINK_FIFO_SIZE_BYTES =
2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3);
+ localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ?
2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of
the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.de> wrote:
> Hi Nate!
>
>
>
> I followed the guide in
> https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus
> ended up with Vivado 2018.3 and then later found out this requires UHD
> 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1
> this would be fixed, but apparently that is not the case. Now I went back
> to 2018.3 (clean re-install) and installed the patch AR#71898. The standard
> N310 image compiles fine now.
>
>
>
> The other error
>
> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
> 'STR_SINK_FIFOSIZE'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>
> seems to be happening only for few specific RFNoC blocks (fosphor and
> split_stream, specifically). Leaving these out, the RFNoC image does
> compile. Not sure what exactly is the problem, though. The recent commit
> https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
> did not help (tried both versions, neither of them works).
>
>
>
> Regards
>
> Robert
>
>
>
>
>
> *From:* Nate Temple [mailto:nate.temple@ettus.com]
> *Sent:* Monday, December 09, 2019 8:43 PM
> *To:* Pöhlmann, Robert
> *Cc:* USRP-users@lists.ettus.com
> *Subject:* Re: [USRP-users] Default RFNoC image for N310 does not compile
>
>
>
> Hi Robert,
>
>
>
> So this is a bug related to Vivado, you will need to install this linked
> below patch and it should resolve it.
>
>
>
> https://www.xilinx.com/support/answers/71898.html
>
>
>
> Regards,
>
> Nate Temple
>
>
>
> On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com> wrote:
>
> Hi Robert,
>
> Thanks for the bug report.
>
> If you're just trying to use RFNoC at this point, I would recommend to
> stick with the latest stable release, which at this time is v3.14.1.1.
>
> Note, 3.14.x.x UHD will require Vivado 2017.4.
>
>
> Regards,
> Nate Temple
>
>
>
> On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> Hi all!
>
>
>
> I tried to compile the default RFNoC image for the N310, using UHD on tag
> v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
>
>
>
> Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but
> then Vivado shows the following errors:
>
>
>
> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
> 'STR_SINK_FIFOSIZE'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
> ERROR: [Synth 8-521] parameter assignment could not be resolved to a
> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
> ERROR: [Synth 8-196] conditional expression could not be resolved to a
> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
> ERROR: [Synth 8-6156] failed synthesizing module
> 'noc_shell__parameterized9'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
> ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
>
>
>
> The full build.log file is attached. I did not modify any files, just
> trying to compile the RFNoC example as provided.
>
>
>
>
>
>
>
> Btw I also tried to build the default image with "make N310_XG", this one
> compiles but failed later during DRC:
>
> [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
> For example, the following two ports in this bank have conflicting VCCOs:
> ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
> (LVCMOS18, requiring VCCO=1.800)
>
> [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
>
>
>
> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
RP
Robert.Poehlmann@dlr.de
Wed, Dec 11, 2019 11:14 AM
Hi Nate,
the image does compile now with the patch. However there still seems to be s.th. wrong on the host side. When running uhd_usrp_probe, it fails when it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID: 0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not _outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
Von: Nate Temple nate.temple@ettus.com
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will be included in the official 3.15.0.0 release:
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8k+7:8k], set_data_bclk[32k+31:32k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
-
localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ? 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.demailto:Robert.Poehlmann@dlr.de> wrote:
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.commailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.commailto:nate.temple@ettus.com> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
USRP-users mailing list
USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Nate,
the image does compile now with the patch. However there still seems to be s.th. wrong on the host side. When running uhd_usrp_probe, it fails when it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID: 0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not _outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
________________________________
Von: Nate Temple <nate.temple@ettus.com>
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will be included in the official 3.15.0.0 release:
---
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8*k+7:8*k], set_data_bclk[32*k+31:32*k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
- localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3);
+ localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ? 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.de<mailto:Robert.Poehlmann@dlr.de>> wrote:
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com<mailto:nate.temple@ettus.com>]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com<mailto:nate.temple@ettus.com>> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
RP
Robert.Poehlmann@dlr.de
Thu, Dec 19, 2019 8:59 AM
Hi Nate,
some news from my side about this issue:
- For v3.15.0.0-rc2, the error shows up when using split_stream or packet_resizer block (and possibly others)
I then followed your advice and went back to v3.14.1.1, which should be stable. Here two problems pop up:
[INFO] [0/PacketResizer_0] Initializing block control (NOC ID: 0x12E5000000000000)
[ERROR] [UHD] Exception caught in safe-call.
in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)0]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Is there a fix available for ctrl_iface.cpp?
Regards,
Robert
Von: Pöhlmann, Robert
Gesendet: Mittwoch, 11. Dezember 2019 12:14:40
An: Nate Temple
Cc: USRP-users@lists.ettus.com
Betreff: AW: [USRP-users] Default RFNoC image for N310 does not compile
Hi Nate,
the image does compile now with the patch. However there still seems to be s.th. wrong on the host side. When running uhd_usrp_probe, it fails when it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID: 0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not _outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
Von: Nate Temple nate.temple@ettus.com
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will be included in the official 3.15.0.0 release:
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8k+7:8k], set_data_bclk[32k+31:32k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
-
localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ? 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.demailto:Robert.Poehlmann@dlr.de> wrote:
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.commailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.commailto:nate.temple@ettus.com> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
USRP-users mailing list
USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Nate,
some news from my side about this issue:
- For v3.15.0.0-rc2, the error shows up when using split_stream or packet_resizer block (and possibly others)
I then followed your advice and went back to v3.14.1.1, which should be stable. Here two problems pop up:
- Timing constraints are no fulfilled (using Viado 2017.4)
- A similar error pops up when probing the device:
[INFO] [0/PacketResizer_0] Initializing block control (NOC ID: 0x12E5000000000000)
[ERROR] [UHD] Exception caught in safe-call.
in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)0]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Is there a fix available for ctrl_iface.cpp?
Regards,
Robert
________________________________
Von: Pöhlmann, Robert
Gesendet: Mittwoch, 11. Dezember 2019 12:14:40
An: Nate Temple
Cc: USRP-users@lists.ettus.com
Betreff: AW: [USRP-users] Default RFNoC image for N310 does not compile
Hi Nate,
the image does compile now with the patch. However there still seems to be s.th. wrong on the host side. When running uhd_usrp_probe, it fails when it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID: 0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not _outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
________________________________
Von: Nate Temple <nate.temple@ettus.com>
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will be included in the official 3.15.0.0 release:
---
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8*k+7:8*k], set_data_bclk[32*k+31:32*k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
- localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3);
+ localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ? 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.de<mailto:Robert.Poehlmann@dlr.de>> wrote:
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com<mailto:nate.temple@ettus.com>]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com<mailto:nate.temple@ettus.com>> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
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EK
EJ Kreinar
Thu, Dec 19, 2019 1:44 PM
The split stream bug seems to have been fixed in October on the master
branch: https://
github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
(but
not yet ported onto 3.14)
I just cherry-picked 1102779f onto my uhd-fpga UHD-3.14 and it cleaned it
up for me.
I assume this will eventually make it to the UHD-3.14 branch? But if not
the cherry pick works fine
EJ
On Thu, Dec 19, 2019, 4:00 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi Nate,
some news from my side about this issue:
- For v3.15.0.0-rc2, the error shows up when using split_stream or
packet_resizer block (and possibly others)
I then followed your advice and went back to v3.14.1.1, which should be
stable. Here two problems pop up:
[INFO] [0/PacketResizer_0] Initializing block control (NOC ID:
0x12E5000000000000)
[ERROR] [UHD] Exception caught in safe-call.
in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with
uhd::endianness_t _endianness = (uhd::endianness_t)0]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl
(CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
[with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError:
Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
[with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Is there a fix available for ctrl_iface.cpp?
Regards,
Robert
Von: Pöhlmann, Robert
Gesendet: Mittwoch, 11. Dezember 2019 12:14:40
An: Nate Temple
Cc: USRP-users@lists.ettus.com
Betreff: AW: [USRP-users] Default RFNoC image for N310 does not compile
Hi Nate,
the image does compile now with the patch. However there still seems to be
s.th. wrong on the host side. When running uhd_usrp_probe, it fails when
it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID:
0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not
_outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
[with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
Von: Nate Temple nate.temple@ettus.com
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will
be included in the official 3.15.0.0 release:
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8k+7:8k],
set_data_bclk[32k+31:32k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
2**(STR_SINK_FIFOSIZE[8k+7:8k]+3);
2**(STR_SINK_FIFOSIZE[8k+7:8k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of
the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM Robert.Poehlmann@dlr.de wrote:
Hi Nate!
I followed the guide in
https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus
ended up with Vivado 2018.3 and then later found out this requires UHD
3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1
this would be fixed, but apparently that is not the case. Now I went back
to 2018.3 (clean re-install) and installed the patch AR#71898. The standard
N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and
split_stream, specifically). Leaving these out, the RFNoC image does
compile. Not sure what exactly is the problem, though. The recent commit
https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked
below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple nate.temple@ettus.com
wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to
stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag
v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully,
but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module
'noc_shell__parameterized9'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just
trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one
compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
(LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
The split stream bug seems to have been fixed in October on the master
branch: https://
github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
(but
not yet ported onto 3.14)
I just cherry-picked 1102779f onto my uhd-fpga UHD-3.14 and it cleaned it
up for me.
I assume this will eventually make it to the UHD-3.14 branch? But if not
the cherry pick works fine
EJ
On Thu, Dec 19, 2019, 4:00 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi Nate,
>
>
> some news from my side about this issue:
>
> - For v3.15.0.0-rc2, the error shows up when using split_stream or
> packet_resizer block (and possibly others)
>
>
> I then followed your advice and went back to v3.14.1.1, which should be
> stable. Here two problems pop up:
>
> - Timing constraints are no fulfilled (using Viado 2017.4)
>
> - A similar error pops up when probing the device:
>
>
> [INFO] [0/PacketResizer_0] Initializing block control (NOC ID:
> 0x12E5000000000000)
> [ERROR] [UHD] Exception caught in safe-call.
> in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with
> uhd::endianness_t _endianness = (uhd::endianness_t)0]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
> this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl
> (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
> unsigned int]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
>
> [ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
> IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError:
> Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
> unsigned int]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
>
> Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
>
>
> Is there a fix available for ctrl_iface.cpp?
>
>
> Regards,
>
> Robert
> ------------------------------
> *Von:* Pöhlmann, Robert
> *Gesendet:* Mittwoch, 11. Dezember 2019 12:14:40
> *An:* Nate Temple
> *Cc:* USRP-users@lists.ettus.com
> *Betreff:* AW: [USRP-users] Default RFNoC image for N310 does not compile
>
>
> Hi Nate,
>
>
> the image does compile now with the patch. However there still seems to be
> s.th. wrong on the host side. When running uhd_usrp_probe, it fails when
> it reaches the split_stream block:
>
>
> [INFO] [0/SplitStream_0] Initializing block control (NOC ID:
> 0x5757000000000000)
> [ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
> IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not
> _outstanding_seqs.empty()
> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
> unsigned int]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
>
> Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
>
>
>
> Regards,
>
> Robert
> ------------------------------
> *Von:* Nate Temple <nate.temple@ettus.com>
> *Gesendet:* Dienstag, 10. Dezember 2019 17:57:20
> *An:* Pöhlmann, Robert
> *Cc:* USRP-users@lists.ettus.com
> *Betreff:* Re: [USRP-users] Default RFNoC image for N310 does not compile
>
> Hi Robert,
>
> This patch/line change detailed below should resolve that issue and will
> be included in the official 3.15.0.0 release:
>
> ---
> usrp3/lib/rfnoc/noc_shell.v | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
> index 927f40a70..732d41afa 100644
> --- a/usrp3/lib/rfnoc/noc_shell.v
> +++ b/usrp3/lib/rfnoc/noc_shell.v
> @@ -267,7 +267,7 @@ module noc_shell
> .o_tdata({set_addr_bclk[8*k+7:8*k],
> set_data_bclk[32*k+31:32*k]}),
> .o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
>
> - localparam [31:0] STR_SINK_FIFO_SIZE_BYTES =
> 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3);
> + localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ?
> 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
> // "Lines" is the most useful unit for the command FIFO size, since
> // commands take either 2 or 3 lines. Software can do the rest of
> the
> // math to figure out how many actual command packets it can send.
>
>
>
> Regards,
> Nate Temple
>
> On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.de> wrote:
>
>> Hi Nate!
>>
>>
>>
>> I followed the guide in
>> https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus
>> ended up with Vivado 2018.3 and then later found out this requires UHD
>> 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1
>> this would be fixed, but apparently that is not the case. Now I went back
>> to 2018.3 (clean re-install) and installed the patch AR#71898. The standard
>> N310 image compiles fine now.
>>
>>
>>
>> The other error
>>
>> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
>> 'STR_SINK_FIFOSIZE'
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>>
>> seems to be happening only for few specific RFNoC blocks (fosphor and
>> split_stream, specifically). Leaving these out, the RFNoC image does
>> compile. Not sure what exactly is the problem, though. The recent commit
>> https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
>> did not help (tried both versions, neither of them works).
>>
>>
>>
>> Regards
>>
>> Robert
>>
>>
>>
>>
>>
>> *From:* Nate Temple [mailto:nate.temple@ettus.com]
>> *Sent:* Monday, December 09, 2019 8:43 PM
>> *To:* Pöhlmann, Robert
>> *Cc:* USRP-users@lists.ettus.com
>> *Subject:* Re: [USRP-users] Default RFNoC image for N310 does not compile
>>
>>
>>
>> Hi Robert,
>>
>>
>>
>> So this is a bug related to Vivado, you will need to install this linked
>> below patch and it should resolve it.
>>
>>
>>
>> https://www.xilinx.com/support/answers/71898.html
>>
>>
>>
>> Regards,
>>
>> Nate Temple
>>
>>
>>
>> On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com>
>> wrote:
>>
>> Hi Robert,
>>
>> Thanks for the bug report.
>>
>> If you're just trying to use RFNoC at this point, I would recommend to
>> stick with the latest stable release, which at this time is v3.14.1.1.
>>
>> Note, 3.14.x.x UHD will require Vivado 2017.4.
>>
>>
>> Regards,
>> Nate Temple
>>
>>
>>
>> On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
>> usrp-users@lists.ettus.com> wrote:
>>
>> Hi all!
>>
>>
>>
>> I tried to compile the default RFNoC image for the N310, using UHD on tag
>> v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
>>
>>
>>
>> Running "make N310_RFNOC_XG", the IP cores are compiled successfully,
>> but then Vivado shows the following errors:
>>
>>
>>
>> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
>> 'STR_SINK_FIFOSIZE'
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>> ERROR: [Synth 8-521] parameter assignment could not be resolved to a
>> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>> ERROR: [Synth 8-196] conditional expression could not be resolved to a
>> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
>> WARNING: [Synth 8-693] zero replication count - replication ignored
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
>> WARNING: [Synth 8-693] zero replication count - replication ignored
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
>> WARNING: [Synth 8-693] zero replication count - replication ignored
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
>> ERROR: [Synth 8-6156] failed synthesizing module
>> 'noc_shell__parameterized9'
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
>> ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
>> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
>> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
>> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
>> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
>> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
>>
>>
>>
>> The full build.log file is attached. I did not modify any files, just
>> trying to compile the RFNoC example as provided.
>>
>>
>>
>>
>>
>>
>>
>> Btw I also tried to build the default image with "make N310_XG", this one
>> compiles but failed later during DRC:
>>
>> [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
>> For example, the following two ports in this bank have conflicting VCCOs:
>> ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
>> (LVCMOS18, requiring VCCO=1.800)
>>
>> [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
>>
>>
>>
>> _______________________________________________
>> USRP-users mailing list
>> USRP-users@lists.ettus.com
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>> _______________________________________________
> USRP-users mailing list
> USRP-users@lists.ettus.com
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
JS
Jeff S
Thu, Dec 19, 2019 4:05 PM
EJ,
I'm finding that I have the same problem after installing 3.14.1.1.
I did the following:
$ uhd_images_downloader
$ uhd_image_loader --args "type=n3xx"
which is what I thought we were supposed to do, but I got the same error on my uhd_usrp_probe that Robert did.
I'll see if I can figure out how to cherry-pick the fpga branch. That may be more research since I have a lot of new stuff I "git" to learn.
Jeff
From: USRP-users usrp-users-bounces@lists.ettus.com on behalf of EJ Kreinar via USRP-users usrp-users@lists.ettus.com
Sent: Thursday, December 19, 2019 7:44 AM
To: Robert.Poehlmann@dlr.de Robert.Poehlmann@dlr.de
Cc: USRP-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
The split stream bug seems to have been fixed in October on the master branch: https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9http://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 (but not yet ported onto 3.14)
I just cherry-picked 1102779f onto my uhd-fpga UHD-3.14 and it cleaned it up for me.
I assume this will eventually make it to the UHD-3.14 branch? But if not the cherry pick works fine
EJ
On Thu, Dec 19, 2019, 4:00 AM Robert via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi Nate,
some news from my side about this issue:
- For v3.15.0.0-rc2, the error shows up when using split_stream or packet_resizer block (and possibly others)
I then followed your advice and went back to v3.14.1.1, which should be stable. Here two problems pop up:
[INFO] [0/PacketResizer_0] Initializing block control (NOC ID: 0x12E5000000000000)
[ERROR] [UHD] Exception caught in safe-call.
in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)0]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Is there a fix available for ctrl_iface.cpp?
Regards,
Robert
Von: Pöhlmann, Robert
Gesendet: Mittwoch, 11. Dezember 2019 12:14:40
An: Nate Temple
Cc: USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
Betreff: AW: [USRP-users] Default RFNoC image for N310 does not compile
Hi Nate,
the image does compile now with the patch. However there still seems to be s.thhttp://s.th. wrong on the host side. When running uhd_usrp_probe, it fails when it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID: 0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not _outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
Von: Nate Temple <nate.temple@ettus.commailto:nate.temple@ettus.com>
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will be included in the official 3.15.0.0 release:
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8k+7:8k], set_data_bclk[32k+31:32k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
-
localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ? 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.demailto:Robert.Poehlmann@dlr.de> wrote:
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.commailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.commailto:nate.temple@ettus.com> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
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EJ,
I'm finding that I have the same problem after installing 3.14.1.1.
I did the following:
$ uhd_images_downloader
$ uhd_image_loader --args "type=n3xx"
which is what I thought we were supposed to do, but I got the same error on my uhd_usrp_probe that Robert did.
I'll see if I can figure out how to cherry-pick the fpga branch. That may be more research since I have a lot of new stuff I "git" to learn.
Jeff
________________________________
From: USRP-users <usrp-users-bounces@lists.ettus.com> on behalf of EJ Kreinar via USRP-users <usrp-users@lists.ettus.com>
Sent: Thursday, December 19, 2019 7:44 AM
To: Robert.Poehlmann@dlr.de <Robert.Poehlmann@dlr.de>
Cc: USRP-users@lists.ettus.com <usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
The split stream bug seems to have been fixed in October on the master branch: https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9<http://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9> (but not yet ported onto 3.14)
I just cherry-picked 1102779f onto my uhd-fpga UHD-3.14 and it cleaned it up for me.
I assume this will eventually make it to the UHD-3.14 branch? But if not the cherry pick works fine
EJ
On Thu, Dec 19, 2019, 4:00 AM Robert via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hi Nate,
some news from my side about this issue:
- For v3.15.0.0-rc2, the error shows up when using split_stream or packet_resizer block (and possibly others)
I then followed your advice and went back to v3.14.1.1, which should be stable. Here two problems pop up:
- Timing constraints are no fulfilled (using Viado 2017.4)
- A similar error pops up when probing the device:
[INFO] [0/PacketResizer_0] Initializing block control (NOC ID: 0x12E5000000000000)
[ERROR] [UHD] Exception caught in safe-call.
in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)0]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError: Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Is there a fix available for ctrl_iface.cpp?
Regards,
Robert
________________________________
Von: Pöhlmann, Robert
Gesendet: Mittwoch, 11. Dezember 2019 12:14:40
An: Nate Temple
Cc: USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
Betreff: AW: [USRP-users] Default RFNoC image for N310 does not compile
Hi Nate,
the image does compile now with the patch. However there still seems to be s.th<http://s.th>. wrong on the host side. When running uhd_usrp_probe, it fails when it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID: 0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError: IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not _outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
________________________________
Von: Nate Temple <nate.temple@ettus.com<mailto:nate.temple@ettus.com>>
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will be included in the official 3.15.0.0 release:
---
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8*k+7:8*k], set_data_bclk[32*k+31:32*k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
- localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3);
+ localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ? 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.de<mailto:Robert.Poehlmann@dlr.de>> wrote:
Hi Nate!
I followed the guide in https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus ended up with Vivado 2018.3 and then later found out this requires UHD 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1 this would be fixed, but apparently that is not the case. Now I went back to 2018.3 (clean re-install) and installed the patch AR#71898. The standard N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and split_stream, specifically). Leaving these out, the RFNoC image does compile. Not sure what exactly is the problem, though. The recent commit https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com<mailto:nate.temple@ettus.com>]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com>
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com<mailto:nate.temple@ettus.com>> wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix 'STR_SINK_FIFOSIZE' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_shell__parameterized9' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor' [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx' [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15] (LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
_______________________________________________
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http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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EK
EJ Kreinar
Thu, Dec 19, 2019 5:28 PM
Ah, Sorry for the confusion. I assume anyone using the split_stream block
is already building FPGA images from source... To clarify, I'm referring to
rebuilding the FPGA images from source using the uhd-fpga repo, which
follows the instructions here:
https://files.ettus.com/manual_archive/v3.14.1.1/html/md_usrp3_build_instructions.html
Depending on the target platform you may also need a Vivado license (or
trial license). You'll want to clone the uhd-fpga repo, then git checkout UHD-3.14, then git cherry-pick 1102779f, THEN build the images.
Definitely a bummer there's not a patched image released. I didnt realize
there were images "in the wild" that used split stream block
EJ
On Thu, Dec 19, 2019 at 11:05 AM Jeff S via USRP-users <
usrp-users@lists.ettus.com> wrote:
EJ,
I'm finding that I have the same problem after installing 3.14.1.1.
I did the following:
$ uhd_images_downloader
$ uhd_image_loader --args "type=n3xx"
which is what I thought we were supposed to do, but I got the same error
on my uhd_usrp_probe that Robert did.
I'll see if I can figure out how to cherry-pick the fpga branch. That may
be more research since I have a lot of new stuff I "git" to learn.
Jeff
From: USRP-users usrp-users-bounces@lists.ettus.com on behalf of EJ
Kreinar via USRP-users usrp-users@lists.ettus.com
Sent: Thursday, December 19, 2019 7:44 AM
To: Robert.Poehlmann@dlr.de Robert.Poehlmann@dlr.de
Cc: USRP-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
The split stream bug seems to have been fixed in October on the master
branch: https://
github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 (but
not yet ported onto 3.14)
I just cherry-picked 1102779f onto my uhd-fpga UHD-3.14 and it cleaned it
up for me.
I assume this will eventually make it to the UHD-3.14 branch? But if not
the cherry pick works fine
EJ
On Thu, Dec 19, 2019, 4:00 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi Nate,
some news from my side about this issue:
- For v3.15.0.0-rc2, the error shows up when using split_stream or
packet_resizer block (and possibly others)
I then followed your advice and went back to v3.14.1.1, which should be
stable. Here two problems pop up:
[INFO] [0/PacketResizer_0] Initializing block control (NOC ID:
0x12E5000000000000)
[ERROR] [UHD] Exception caught in safe-call.
in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with
uhd::endianness_t _endianness = (uhd::endianness_t)0]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl
(CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
[with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError:
Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
[with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Is there a fix available for ctrl_iface.cpp?
Regards,
Robert
Von: Pöhlmann, Robert
Gesendet: Mittwoch, 11. Dezember 2019 12:14:40
An: Nate Temple
Cc: USRP-users@lists.ettus.com
Betreff: AW: [USRP-users] Default RFNoC image for N310 does not compile
Hi Nate,
the image does compile now with the patch. However there still seems to be
s.th. wrong on the host side. When running uhd_usrp_probe, it fails when
it reaches the split_stream block:
[INFO] [0/SplitStream_0] Initializing block control (NOC ID:
0x5757000000000000)
[ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not
_outstanding_seqs.empty()
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
[with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
unsigned int]
at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
Regards,
Robert
Von: Nate Temple nate.temple@ettus.com
Gesendet: Dienstag, 10. Dezember 2019 17:57:20
An: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Betreff: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
This patch/line change detailed below should resolve that issue and will
be included in the official 3.15.0.0 release:
usrp3/lib/rfnoc/noc_shell.v | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
index 927f40a70..732d41afa 100644
--- a/usrp3/lib/rfnoc/noc_shell.v
+++ b/usrp3/lib/rfnoc/noc_shell.v
@@ -267,7 +267,7 @@ module noc_shell
.o_tdata({set_addr_bclk[8k+7:8k],
set_data_bclk[32k+31:32k]}),
.o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
2**(STR_SINK_FIFOSIZE[8k+7:8k]+3);
2**(STR_SINK_FIFOSIZE[8k+7:8k]+3) : 0;
// "Lines" is the most useful unit for the command FIFO size, since
// commands take either 2 or 3 lines. Software can do the rest of
the
// math to figure out how many actual command packets it can send.
Regards,
Nate Temple
On Tue, Dec 10, 2019 at 8:46 AM Robert.Poehlmann@dlr.de wrote:
Hi Nate!
I followed the guide in
https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus
ended up with Vivado 2018.3 and then later found out this requires UHD
3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1
this would be fixed, but apparently that is not the case. Now I went back
to 2018.3 (clean re-install) and installed the patch AR#71898. The standard
N310 image compiles fine now.
The other error
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
seems to be happening only for few specific RFNoC blocks (fosphor and
split_stream, specifically). Leaving these out, the RFNoC image does
compile. Not sure what exactly is the problem, though. The recent commit
https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
did not help (tried both versions, neither of them works).
Regards
Robert
From: Nate Temple [mailto:nate.temple@ettus.com]
Sent: Monday, December 09, 2019 8:43 PM
To: Pöhlmann, Robert
Cc: USRP-users@lists.ettus.com
Subject: Re: [USRP-users] Default RFNoC image for N310 does not compile
Hi Robert,
So this is a bug related to Vivado, you will need to install this linked
below patch and it should resolve it.
https://www.xilinx.com/support/answers/71898.html
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 10:38 AM Nate Temple nate.temple@ettus.com wrote:
Hi Robert,
Thanks for the bug report.
If you're just trying to use RFNoC at this point, I would recommend to
stick with the latest stable release, which at this time is v3.14.1.1.
Note, 3.14.x.x UHD will require Vivado 2017.4.
Regards,
Nate Temple
On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi all!
I tried to compile the default RFNoC image for the N310, using UHD on tag
v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but
then Vivado shows the following errors:
ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
'STR_SINK_FIFOSIZE'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-521] parameter assignment could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
ERROR: [Synth 8-196] conditional expression could not be resolved to a
constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
WARNING: [Synth 8-693] zero replication count - replication ignored
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
ERROR: [Synth 8-6156] failed synthesizing module
'noc_shell__parameterized9'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
[/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
[/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
The full build.log file is attached. I did not modify any files, just
trying to compile the RFNoC example as provided.
Btw I also tried to build the default image with "make N310_XG", this one
compiles but failed later during DRC:
[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
For example, the following two ports in this bank have conflicting VCCOs:
ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
(LVCMOS18, requiring VCCO=1.800)
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
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Ah, Sorry for the confusion. I assume anyone using the split_stream block
is already building FPGA images from source... To clarify, I'm referring to
rebuilding the FPGA images from source using the uhd-fpga repo, which
follows the instructions here:
https://files.ettus.com/manual_archive/v3.14.1.1/html/md_usrp3_build_instructions.html
Depending on the target platform you may also need a Vivado license (or
trial license). You'll want to clone the uhd-fpga repo, then `git checkout
UHD-3.14`, then `git cherry-pick 1102779f`, THEN build the images.
Definitely a bummer there's not a patched image released. I didnt realize
there were images "in the wild" that used split stream block
EJ
On Thu, Dec 19, 2019 at 11:05 AM Jeff S via USRP-users <
usrp-users@lists.ettus.com> wrote:
> EJ,
>
> I'm finding that I have the same problem after installing 3.14.1.1.
>
> I did the following:
>
> $ uhd_images_downloader
> $ uhd_image_loader --args "type=n3xx"
>
>
> which is what I thought we were supposed to do, but I got the same error
> on my uhd_usrp_probe that Robert did.
>
> I'll see if I can figure out how to cherry-pick the fpga branch. That may
> be more research since I have a lot of new stuff I "git" to learn.
>
> Jeff
>
>
> ------------------------------
> *From:* USRP-users <usrp-users-bounces@lists.ettus.com> on behalf of EJ
> Kreinar via USRP-users <usrp-users@lists.ettus.com>
> *Sent:* Thursday, December 19, 2019 7:44 AM
> *To:* Robert.Poehlmann@dlr.de <Robert.Poehlmann@dlr.de>
> *Cc:* USRP-users@lists.ettus.com <usrp-users@lists.ettus.com>
> *Subject:* Re: [USRP-users] Default RFNoC image for N310 does not compile
>
> The split stream bug seems to have been fixed in October on the master
> branch: https://
> github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9 (but
> not yet ported onto 3.14)
>
> I just cherry-picked 1102779f onto my uhd-fpga UHD-3.14 and it cleaned it
> up for me.
>
> I assume this will eventually make it to the UHD-3.14 branch? But if not
> the cherry pick works fine
>
> EJ
>
> On Thu, Dec 19, 2019, 4:00 AM Robert via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> Hi Nate,
>
>
> some news from my side about this issue:
>
> - For v3.15.0.0-rc2, the error shows up when using split_stream or
> packet_resizer block (and possibly others)
>
>
> I then followed your advice and went back to v3.14.1.1, which should be
> stable. Here two problems pop up:
>
> - Timing constraints are no fulfilled (using Viado 2017.4)
>
> - A similar error pops up when probing the device:
>
>
> [INFO] [0/PacketResizer_0] Initializing block control (NOC ID:
> 0x12E5000000000000)
> [ERROR] [UHD] Exception caught in safe-call.
> in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with
> uhd::endianness_t _endianness = (uhd::endianness_t)0]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:52
> this->send_cmd_pkt(0, 0, true); -> EnvironmentError: IOError: Block ctrl
> (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
> unsigned int]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
>
> [ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
> IOError: [0/PacketResizer_0] sr_read64() failed: EnvironmentError: IOError:
> Block ctrl (CE_10_Port_D0) no response packet - AssertionError: bool(buff)
> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
> unsigned int]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:142
>
> Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
>
>
> Is there a fix available for ctrl_iface.cpp?
>
>
> Regards,
>
> Robert
> ------------------------------
> *Von:* Pöhlmann, Robert
> *Gesendet:* Mittwoch, 11. Dezember 2019 12:14:40
> *An:* Nate Temple
> *Cc:* USRP-users@lists.ettus.com
> *Betreff:* AW: [USRP-users] Default RFNoC image for N310 does not compile
>
>
> Hi Nate,
>
>
> the image does compile now with the patch. However there still seems to be
> s.th. wrong on the host side. When running uhd_usrp_probe, it fails when
> it reaches the split_stream block:
>
>
> [INFO] [0/SplitStream_0] Initializing block control (NOC ID:
> 0x5757000000000000)
> [ERROR] [MPMD] Failure during block enumeration: EnvironmentError:
> IOError: [0/SplitStream_0] sr_write() failed: AssertionError: not
> _outstanding_seqs.empty()
> in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double)
> [with uhd::endianness_t _endianness = (uhd::endianness_t)0; uint64_t = long
> unsigned int]
> at /usr/local/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:139
>
> Error: RuntimeError: Failed to run enumerate_rfnoc_blocks()
>
>
>
> Regards,
>
> Robert
> ------------------------------
> *Von:* Nate Temple <nate.temple@ettus.com>
> *Gesendet:* Dienstag, 10. Dezember 2019 17:57:20
> *An:* Pöhlmann, Robert
> *Cc:* USRP-users@lists.ettus.com
> *Betreff:* Re: [USRP-users] Default RFNoC image for N310 does not compile
>
> Hi Robert,
>
> This patch/line change detailed below should resolve that issue and will
> be included in the official 3.15.0.0 release:
>
> ---
> usrp3/lib/rfnoc/noc_shell.v | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/usrp3/lib/rfnoc/noc_shell.v b/usrp3/lib/rfnoc/noc_shell.v
> index 927f40a70..732d41afa 100644
> --- a/usrp3/lib/rfnoc/noc_shell.v
> +++ b/usrp3/lib/rfnoc/noc_shell.v
> @@ -267,7 +267,7 @@ module noc_shell
> .o_tdata({set_addr_bclk[8*k+7:8*k],
> set_data_bclk[32*k+31:32*k]}),
> .o_tvalid(set_stb_bclk[k]), .o_tready(set_stb_bclk[k]));
>
> - localparam [31:0] STR_SINK_FIFO_SIZE_BYTES =
> 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3);
> + localparam [31:0] STR_SINK_FIFO_SIZE_BYTES = (k < INPUT_PORTS) ?
> 2**(STR_SINK_FIFOSIZE[8*k+7:8*k]+3) : 0;
> // "Lines" is the most useful unit for the command FIFO size, since
> // commands take either 2 or 3 lines. Software can do the rest of
> the
> // math to figure out how many actual command packets it can send.
>
>
>
> Regards,
> Nate Temple
>
> On Tue, Dec 10, 2019 at 8:46 AM <Robert.Poehlmann@dlr.de> wrote:
>
> Hi Nate!
>
>
>
> I followed the guide in
> https://files.ettus.com/manual/md_usrp3_build_instructions.html, thus
> ended up with Vivado 2018.3 and then later found out this requires UHD
> 3.15. Thanks for pointing me to the Vivado bug. I thought with 2018.3.1
> this would be fixed, but apparently that is not the case. Now I went back
> to 2018.3 (clean re-install) and installed the patch AR#71898. The standard
> N310 image compiles fine now.
>
>
>
> The other error
>
> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
> 'STR_SINK_FIFOSIZE'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
>
> seems to be happening only for few specific RFNoC blocks (fosphor and
> split_stream, specifically). Leaving these out, the RFNoC image does
> compile. Not sure what exactly is the problem, though. The recent commit
> https://github.com/EttusResearch/fpga/commit/1102779f49d44c9e8b88ce7251d203eb62ae26c9
> did not help (tried both versions, neither of them works).
>
>
>
> Regards
>
> Robert
>
>
>
>
>
> *From:* Nate Temple [mailto:nate.temple@ettus.com]
> *Sent:* Monday, December 09, 2019 8:43 PM
> *To:* Pöhlmann, Robert
> *Cc:* USRP-users@lists.ettus.com
> *Subject:* Re: [USRP-users] Default RFNoC image for N310 does not compile
>
>
>
> Hi Robert,
>
>
>
> So this is a bug related to Vivado, you will need to install this linked
> below patch and it should resolve it.
>
>
>
> https://www.xilinx.com/support/answers/71898.html
>
>
>
> Regards,
>
> Nate Temple
>
>
>
> On Mon, Dec 9, 2019 at 10:38 AM Nate Temple <nate.temple@ettus.com> wrote:
>
> Hi Robert,
>
> Thanks for the bug report.
>
> If you're just trying to use RFNoC at this point, I would recommend to
> stick with the latest stable release, which at this time is v3.14.1.1.
>
> Note, 3.14.x.x UHD will require Vivado 2017.4.
>
>
> Regards,
> Nate Temple
>
>
>
> On Mon, Dec 9, 2019 at 7:33 AM Robert via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
> Hi all!
>
>
>
> I tried to compile the default RFNoC image for the N310, using UHD on tag
> v3.15.0.0-rc2 and Xilinx Vivado 2018.3.1.
>
>
>
> Running "make N310_RFNOC_XG", the IP cores are compiled successfully, but
> then Vivado shows the following errors:
>
>
>
> ERROR: [Synth 8-524] part-select [15:8] out of range of prefix
> 'STR_SINK_FIFOSIZE'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
> ERROR: [Synth 8-521] parameter assignment could not be resolved to a
> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:270]
> ERROR: [Synth 8-196] conditional expression could not be resolved to a
> constant [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:239]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:26]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:27]
> WARNING: [Synth 8-693] zero replication count - replication ignored
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:31]
> ERROR: [Synth 8-6156] failed synthesizing module
> 'noc_shell__parameterized9'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v:21]
> ERROR: [Synth 8-6156] failed synthesizing module 'noc_block_fosphor'
> [/usr/local/src/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fosphor.v:8]
> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx_core'
> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/n3xx_core.v:17]
> ERROR: [Synth 8-6156] failed synthesizing module 'n3xx'
> [/usr/local/src/uhd/fpga-src/usrp3/top/n3xx/dboards/mg/n3xx.v:13]
>
>
>
> The full build.log file is attached. I did not modify any files, just
> trying to compile the RFNoC example as provided.
>
>
>
>
>
>
>
> Btw I also tried to build the default image with "make N310_XG", this one
> compiles but failed later during DRC:
>
> [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 34.
> For example, the following two ports in this bank have conflicting VCCOs:
> ddr3_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and ddr3_addr[15]
> (LVCMOS18, requiring VCCO=1.800)
>
> [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.
>
>
>
> _______________________________________________
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>
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>
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>
