While doing some tests using a pd16 (5/10 MHz to 1,10,100,1000 Hz output) I noticed the 10 and 100 Hz outputs seemed to do a small phase shift every 5 counts I measured 400 ps shift every 5 counts for the 10 Hz output and about 800 ps shift every 5 counts for the 100 Hz output. To verify the test setup I used a pd05 (10 MHz to 100 Hz) and this did not show the phase shift every 5 counts. Is this phase shift to be expected from all multiple output frequency picDIV's ? Erik.

Hi Erik -- It's possible you're seeing cross-talk across the outputs. On the TADD-2 which uses a PIC divider that is similar to what you describe, each of the outputs drives three of the six gates of a 74AC04 inverter, and the two halves of the '04 are driven at different output rates, you can see some artifacts on the slower side. The coupling might come from the board layout, from coupling within the chip, or bounce on the Vcc, particularly if the buffers are driving a low Z load. So I'd suggest measuring as close to the PIC pins as possible with TTL-like (not 50Z) loads on all outputs, and also looking at the decoupling of the PIC power pin. John ---- On 5/3/24 07:23, Erik Kaashoek via time-nuts wrote: > While doing some tests using a pd16 (5/10 MHz to 1,10,100,1000 Hz > output) I noticed the 10 and 100 Hz outputs seemed to do a small phase > shift every 5 counts > I measured 400 ps shift every 5 counts for the 10 Hz output and about > 800 ps shift every 5 counts for the 100 Hz output. > To verify the test setup I used a pd05 (10 MHz to 100 Hz) and this did > not show the phase shift every 5 counts. > Is this phase shift to be expected from all multiple output frequency > picDIV's ? > Erik. > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe send an email to time-nuts-leave@lists.febo.com