Network interface cards that support timestamping
Hi
Yet again, back to: what is the goal?
For NTP, you have a range of numbers To a great degree they are limited by the network
nonsense that may (or may not) be going on. A 12ps NTP logging process likely does not
do much for a network that has 12 ms of nonsense going on.
PTP may / will / might / should fix some of that stuff. Unfortunately there is a “maybe” that
qualifies all of that.
Welcome to the real world, all sorts of bad stuff happens.
Bob
On Jan 30, 2023, at 6:18 PM, S McGrath via time-nuts time-nuts@lists.febo.com wrote:
Driving Pin1 only works with a ‘real’ serial port on a dedicated IRQ. a
USB interface will add unpredictable latency
On Mon, Jan 30, 2023 at 6:16 PM Lux, Jim via time-nuts <
time-nuts@lists.febo.com> wrote:
On 1/30/23 12:28 PM, S McGrath via time-nuts wrote:
Most common way of getting 1PPS into a computer without a dedicated 1PPS
interface is to drive a RS-232 port’s Carrier Detect pin (pin 1 on DB-9)
with the 1PPS signal
back in the day when that tied directly to an interrupt with consistent
latency, that works pretty well.
These days, though, there's often USB hosts in the way, or some other
intermediate interfaces that increases the uncertainty in timing of
"when software does something" in response to "external event"
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On 1/30/23 5:31 PM, S McGrath via time-nuts wrote:
All your points are good ones, My point was this is the common lowest
cost approach, better approaches exist and they range from tens of dollars
to thousands depending on the accuracy needed.
Driving the CD line with a ‘real’ serial port is good enough for ‘standard’
NTP timing applications, its not good enough for a ‘time nuts’
implementation
I daresay that finding a motherboard with a "real" serial port is pretty
challenging. And even if you plugged in a serial expansion card of some
sort, modern mobos probably aren't going to have a clean deterministic
IRQ behavior.
The idea of a (potentially inexpensive) standalone box that can do it is
intriguing. But we started with networking - So what is being discussed
is something like a USB Ethernet dongle with time stamping.
John-
I brought this up once before. White Rabbit research has shown to do sync
well you need BIDI fiber SFPs. Two wavelengths going opposite directions
down the same single mode fiber. See:
https://ohwr.org/project/white-rabbit/wikis/SFP
The new future of nics that do this type of timing sync are DPU's.
https://www.nvidia.com/content/dam/en-zz/Solutions/gtcf21/networking/data-processing-unit/gtc-fall-21-networking-overall-dpu-technical-overview-firefly.pdf
I'm really interested in precision PTP over Ethernet over fiber.
Kinda related... Meta is looking at timebeat and I recently posted about
the new cards they're selling with MEMS DCOCXO SiT5721 for holdover.
Seems the future of Ethernet timing sync time stamping is developing well
right now. Fiber is the way to go though.
Bill
On Mon, Jan 30, 2023, 9:18 PM Lux, Jim via time-nuts <
time-nuts@lists.febo.com> wrote:
On 1/30/23 5:31 PM, S McGrath via time-nuts wrote:
All your points are good ones, My point was this is the common lowest
cost approach, better approaches exist and they range from tens of
dollars
to thousands depending on the accuracy needed.
Driving the CD line with a ‘real’ serial port is good enough for
‘standard’
NTP timing applications, its not good enough for a ‘time nuts’
implementation
I daresay that finding a motherboard with a "real" serial port is pretty
challenging. And even if you plugged in a serial expansion card of some
sort, modern mobos probably aren't going to have a clean deterministic
IRQ behavior.
The idea of a (potentially inexpensive) standalone box that can do it is
intriguing. But we started with networking - So what is being discussed
is something like a USB Ethernet dongle with time stamping.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe send an email to time-nuts-leave@lists.febo.com
It’s too bad the SiT5721 is over $135 in 25 quantity orders. That prices it above a used but not used up rubidium.
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From: Bill Notfaded via time-nuts time-nuts@lists.febo.com
Sent: Tuesday, January 31, 2023 5:21:04 AM
To: Discussion of precise time and frequency measurement time-nuts@lists.febo.com
Cc: Bill Notfaded notfaded1@gmail.com
Subject: [time-nuts] Re: Network interface cards that support timestamping
John-
I brought this up once before. White Rabbit research has shown to do sync
well you need BIDI fiber SFPs. Two wavelengths going opposite directions
down the same single mode fiber. See:
https://ohwr.org/project/white-rabbit/wikis/SFP
The new future of nics that do this type of timing sync are DPU's.
https://www.nvidia.com/content/dam/en-zz/Solutions/gtcf21/networking/data-processing-unit/gtc-fall-21-networking-overall-dpu-technical-overview-firefly.pdf
I'm really interested in precision PTP over Ethernet over fiber.
Kinda related... Meta is looking at timebeat and I recently posted about
the new cards they're selling with MEMS DCOCXO SiT5721 for holdover.
Seems the future of Ethernet timing sync time stamping is developing well
right now. Fiber is the way to go though.
Bill
On Mon, Jan 30, 2023, 9:18 PM Lux, Jim via time-nuts <
time-nuts@lists.febo.com> wrote:
On 1/30/23 5:31 PM, S McGrath via time-nuts wrote:
All your points are good ones, My point was this is the common lowest
cost approach, better approaches exist and they range from tens of
dollars
to thousands depending on the accuracy needed.
Driving the CD line with a ‘real’ serial port is good enough for
‘standard’
NTP timing applications, its not good enough for a ‘time nuts’
implementation
I daresay that finding a motherboard with a "real" serial port is pretty
challenging. And even if you plugged in a serial expansion card of some
sort, modern mobos probably aren't going to have a clean deterministic
IRQ behavior.
The idea of a (potentially inexpensive) standalone box that can do it is
intriguing. But we started with networking - So what is being discussed
is something like a USB Ethernet dongle with time stamping.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe send an email to time-nuts-leave@lists.febo.com
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To unsubscribe send an email to time-nuts-leave@lists.febo.com
Despite hardware timestampers being common on microcontrollers, SoCs that
can run Linux never seem to have them.
BeagleBone Black does run Linux and has timer capture hardware, though it's
a bit 'slow' it's still available. Dan Drown (originally) also wrote a PPS
module targeting it, though it's been unmaintained (
https://github.com/thinkfat/pps-gmtimer was the closest fork to working for
me, but it still required some fiddling around with DeviceTree etc. ). It
tries to pull the somewhat clever trick of switching the system's clock
source to the capture timer, and then copying the capture value directly
into the PPS report, which in theory should be about as good a capture as
you could get - no polling the kernel timestamp or the input pin. I've been
running this for a while with a GPSDO as PPS source, and while the average
offset reported by chrony is single-digit ns, there are occasional spikes
to 100s of ns.
The NIC also does have hardware timestamping functionality for PTP.
On Mon, 30 Jan 2023 at 18:26, Trent Piepho via time-nuts <
time-nuts@lists.febo.com> wrote:
Even if you have a real serial port, still common in embedded SoCs that run
Linux if not on PCs, and even if it still has a CD line to generate an
interrupt, there are still issues.
Modern CPUs are complex, and while the serial port might even be on the
same chip as the CPU, they are connected through an internal network like
an AXI bus that adds latency and jitter. A PCI-E network card generating
an interrupt still needs to send a MSI packet over the PCI-E network bus to
the PCI-E controller, which then needs to send it on the CPU through some
other kind of internal network.
But that's not even the bad part. Once the CPU gets an interrupt, there is
still a lot of stuff that needs to happen in software before a timestamp is
generated. The CPU must context switch, new cachline loads from RAM for
data and code, the base kernel interrupt dispatching, etc.
With tests I did a while back with GPS PPS on an embedded Linux board, this
was the largest source of error.
Despite hardware timestampers being common on microcontrollers, SoCs that
can run Linux never seem to have them.
I wonder if one could make a useful USB timestamper with a common USB
microcontroller board. These have hardware counters that can timestamp a
PPS. It would be easy to send these timestamps over USB. Not sending
events about a PPS, but sending the actual timestamp of the PPS. USB has,
comparatively, terrible timing jitter, so timestamping the arrival of a USB
packet is of course no good.
With a bit of thought, we might think this is a step back. We have GPS
with an accurate clock that sends NMEA timestamps to us over an inaccurate
UART. Now we have a microcontroller with a semi-accurate clock sending
timestamps to us over an even more inaccurate USB interface. Same problem,
but worse.
But there is a difference! Typically the clock in an USB connected
microcontroller can use USB clock recovery. It's disciplined to the 1kHz
USB SOF signal from the host computer. This lets them meet the USB timing
spec with a cheap internal resonator.
So the clock in the microcontroller that gives us timestamps is in fact
tracking our clock. Does that make a difference? We can infer that the
error in the timestamps we get reflects a matching error in the host clock
we are trying to discipline with the PPS.
On Mon, Jan 30, 2023 at 4:01 PM S McGrath via time-nuts <
time-nuts@lists.febo.com> wrote:
Driving Pin1 only works with a ‘real’ serial port on a dedicated IRQ. a
USB interface will add unpredictable latency
On Mon, Jan 30, 2023 at 6:16 PM Lux, Jim via time-nuts <
time-nuts@lists.febo.com> wrote:
On 1/30/23 12:28 PM, S McGrath via time-nuts wrote:
Most common way of getting 1PPS into a computer without a dedicated
1PPS
interface is to drive a RS-232 port’s Carrier Detect pin (pin 1 on
DB-9)
with the 1PPS signal
back in the day when that tied directly to an interrupt with consistent
latency, that works pretty well.
These days, though, there's often USB hosts in the way, or some other
intermediate interfaces that increases the uncertainty in timing of
"when software does something" in response to "external event"
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe send an email to time-nuts-leave@lists.febo.com
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To unsubscribe send an email to time-nuts-leave@lists.febo.com
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I get the impression from a cursory search that the card might take either a PPS or a 10 MHz, and that to get it to function as a PTP server that it probably needs a specific FPGA image and/or driver
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From: John Miller via time-nuts time-nuts@lists.febo.com
Sent: Monday, January 30, 2023 12:15:27 PM
To: Discussion of precise time and frequency measurement time-nuts@lists.febo.com
Cc: John Miller john@millerjs.org
Subject: [time-nuts] Network interface cards that support timestamping
Hey All,
I'm curious as to what the collective experience is amongst this group when it comes to feeding a timestamp signal into a NIC, either for PTP purposes or for as a normal PPS refclock. The Intel i210 PCIe network card has a few software defined pins that can be used for this purpose, and the chrony documentation has some information about it:
https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic
I imagine most of us here use traditional RS232 serial ports to get this signal into an x86 computer, usually using the DCD pin. I've found some implementations of RS232 on PCs don't implement all of the additional signaling pins, so sometimes DCD is flat out missing. In other cases - especially with smaller embedded-type boards only UARTs with Rx/Tx are available to the user. (I'm fiddling with using GPIO pins on a few such systems, but it's quite a struggle.) So, there is a need for getting PPS signals into systems.
There are also highly specialized network interface cards, such as this one: https://www.ebay.com/itm/404117321209
... which does explicitly support PTP timestamping, but it's not clear to me if it could pull in a "standard" PPS signal to be made available to chrony or NTPsec. I haven't found much documentation on the NT20E2 yet, unfortunately, and it may simply not exist for hobbyists.
Does anyone here know if any other network cards that support software defined pins, like the i210 does, or any other methods for getting a PPS signal to be fed into a PC, and of course interpreted correctly?
Thanks!
John
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On 1/30/23 10:15 AM, John Miller via time-nuts wrote:
Hey All,
I'm curious as to what the collective experience is amongst this group when it comes to feeding a timestamp signal into a NIC, either for PTP purposes or for as a normal PPS refclock. The Intel i210 PCIe network card has a few software defined pins that can be used for this purpose, and the chrony documentation has some information about it:
https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic
I imagine most of us here use traditional RS232 serial ports to get this signal into an x86 computer, usually using the DCD pin. I've found some implementations of RS232 on PCs don't implement all of the additional signaling pins, so sometimes DCD is flat out missing. In other cases - especially with smaller embedded-type boards only UARTs with Rx/Tx are available to the user. (I'm fiddling with using GPIO pins on a few such systems, but it's quite a struggle.) So, there is a need for getting PPS signals into systems.
There are also highly specialized network interface cards, such as this one: https://www.ebay.com/itm/404117321209
... which does explicitly support PTP timestamping, but it's not clear to me if it could pull in a "standard" PPS signal to be made available to chrony or NTPsec. I haven't found much documentation on the NT20E2 yet, unfortunately, and it may simply not exist for hobbyists.
Does anyone here know if any other network cards that support software defined pins, like the i210 does, or any other methods for getting a PPS signal to be fed into a PC, and of course interpreted correctly?
A friend pointed me at this thread, I just finished hooking up 2 i211s to two separate u-blox
receivers to rather good effect. Specifically, I have an APU2 and hooked up the receivers as
described at [1]. Note that it doesn't actually matter which of the four pins you hook it up to, any
can be configured to interrupt (though you need the patch at [2] for recent kernels).
The serials on the same board come in via a Nuvoton NCT5104D LPC <-> 4xCOM port chip (which I assume
is probably not uncommon for many machines these days). The same GPS receivers were hooked up via
that via DCD pins, which were properly interrupt'ing but had jitter on the order of 10-25us. Chrony
would often report a bit less std dev across a few samples, but the two receivers would wander
around the current time and often by off in different directions. With the receivers moved over to
the i211s chrony now reports std dev between 5 and 100ns, though given they're always off in the
same direction on a similar order of magnitude I think that's the system clock being off more than
interrupt latency.
You can find graphs at [3], though excuse the lack of history, I re-soldered a few hours ago and am
still testing it so dropping data since last boot.
While the i211 theoretically supports both interrupting for the Software-Defined-Pins and packet
timestamping for PTP (and NTP) purposes, it is entirely unclear to me if chrony uses the NIC clock
to respond to NTP. chrony happily accepts the hwtimestamping option for the NICs and correctly reads
from the NIC's PPS pin as a PHC clock, but there doesn't seem to be any config to hook the two up
somehow.
The testptp utility in the kernel source tree tells me that it takes 8000-9000ns to read the NIC's
clock, and chrony pretty reliably reports the +/- on a sample from the NIC PPS as +/- 1100-1200ns so
it lines up that there's around 1000ns of jitter on the interrupt.
Matt
[1] https://blog.dan.drown.org/apu2-ntp-server-2/
[2] https://lists.osuosl.org/pipermail/intel-wired-lan/Week-of-Mon-20230130/031970.html
[3] https://noc.as397444.net/ntpgraphs.day/
Hi Matt,
This is excellent information, thank you - after reading through all the responses in the thread (wow, this is a wild topic!) and trawling around online a bit, I think that using the SDP pins on the i210 to feed a PPS signal into an x86 PC is what I want to do right now.
I have read Dan Drown's blog post on using the APU2 to achieve this, and while it's more or less exactly what I want to replicate, for now, there are a few gaps I need to fill in - and you may be able to help me do so. I don't have a PC Engines APU2 board yet, but I suspect I'll order one once I have the software side of things ironed out, because I really like their form factor.
What I'm using right now is a Portwell NANO-6050[1], and it has i210 and i218 NICs. The SDP pins on the i210 aren't broken out into nice pads like the APU2 has, but with some magnet wire and a steady hand I was able to connect directly to one of the pins. Where I am struggling right now is ironing out the software configuration side of things. I'm not interested at all in PTP yet, right now the focus is purely on feeding the PPS into chrony via the SDP pins. The GNSS I'm using is a Sparkfun uBlox NEO-M9N GNSS receiver in its default configuration, connected to the computer over USB. PPS pin connected to the i210's SDP0. PPS pulse is 3v3 for 100ms.
I have tried using refclock strings from chrony's examples page[2] as a jumping-off point, but it doesn't make much sense to me. 16Hz PPS with a rate of 16 - why not use 1Hz with a default rate of 1? The Dan Drown blog post makes a little bit more sense, but I think something is missing from the 'relevant chrony.conf' example - notably, it includes a single refclock line with the "pps" option, which according to the chrony.conf docs[4]: "Another time source is needed to complete samples from the refclock." and that example isn't included. Furthermore, his "width" parameter is set to 0.7 milliseconds, which seems tremendously short to me. If the PPS pulses are 100ms (which I understand to be fairly standard) why wouldn't the width be configured as such? I may be misunderstanding this parameter.
Either way, am not able to get chrony to lock up to a PHC refclock.[5] This is what my chrony.conf looks like: https://paste.millerjs.org/ajoxigiquc.txt
I have not been able to use the testptp tool on this system yet - building it on another machine and running the copied-over executable fails, citing too old a version of glibc, and when I try and build it locally it fails for reasons that are unknown to me (I am very much not a C developer). I may have to install a newer OS in order to try this out.
I am going to continue to fiddle with this - I think getting testptp working such that I can verify that I'm actually getting a pulse on SDP0 is the most important thing to confirm right now. I would greatly appreciate any help or feedback!
Thanks,
John
KC1QLN
[1] https://portwell.com/products/detail.php?CUSTCHAR1=NANO-6050
[2] https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic
[3] https://blog.dan.drown.org/apu2-ntp-server-2/
[4] https://chrony.tuxfamily.org/doc/4.3/chrony.conf.html
[5] https://paste.millerjs.org/edebutayoz.txt
On Jan 31, 2023, at 9:43 PM, Matt Corallo timenuts-list@mattcorallo.com wrote:
On 1/30/23 10:15 AM, John Miller via time-nuts wrote:
Hey All,
I'm curious as to what the collective experience is amongst this group when it comes to feeding a timestamp signal into a NIC, either for PTP purposes or for as a normal PPS refclock. The Intel i210 PCIe network card has a few software defined pins that can be used for this purpose, and the chrony documentation has some information about it:
https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic
I imagine most of us here use traditional RS232 serial ports to get this signal into an x86 computer, usually using the DCD pin. I've found some implementations of RS232 on PCs don't implement all of the additional signaling pins, so sometimes DCD is flat out missing. In other cases - especially with smaller embedded-type boards only UARTs with Rx/Tx are available to the user. (I'm fiddling with using GPIO pins on a few such systems, but it's quite a struggle.) So, there is a need for getting PPS signals into systems.
There are also highly specialized network interface cards, such as this one: https://www.ebay.com/itm/404117321209
... which does explicitly support PTP timestamping, but it's not clear to me if it could pull in a "standard" PPS signal to be made available to chrony or NTPsec. I haven't found much documentation on the NT20E2 yet, unfortunately, and it may simply not exist for hobbyists.
Does anyone here know if any other network cards that support software defined pins, like the i210 does, or any other methods for getting a PPS signal to be fed into a PC, and of course interpreted correctly?
A friend pointed me at this thread, I just finished hooking up 2 i211s to two separate u-blox receivers to rather good effect. Specifically, I have an APU2 and hooked up the receivers as described at [1]. Note that it doesn't actually matter which of the four pins you hook it up to, any can be configured to interrupt (though you need the patch at [2] for recent kernels).
The serials on the same board come in via a Nuvoton NCT5104D LPC <-> 4xCOM port chip (which I assume is probably not uncommon for many machines these days). The same GPS receivers were hooked up via that via DCD pins, which were properly interrupt'ing but had jitter on the order of 10-25us. Chrony would often report a bit less std dev across a few samples, but the two receivers would wander around the current time and often by off in different directions. With the receivers moved over to the i211s chrony now reports std dev between 5 and 100ns, though given they're always off in the same direction on a similar order of magnitude I think that's the system clock being off more than interrupt latency.
You can find graphs at [3], though excuse the lack of history, I re-soldered a few hours ago and am still testing it so dropping data since last boot.
While the i211 theoretically supports both interrupting for the Software-Defined-Pins and packet timestamping for PTP (and NTP) purposes, it is entirely unclear to me if chrony uses the NIC clock to respond to NTP. chrony happily accepts the hwtimestamping option for the NICs and correctly reads from the NIC's PPS pin as a PHC clock, but there doesn't seem to be any config to hook the two up somehow.
The testptp utility in the kernel source tree tells me that it takes 8000-9000ns to read the NIC's clock, and chrony pretty reliably reports the +/- on a sample from the NIC PPS as +/- 1100-1200ns so it lines up that there's around 1000ns of jitter on the interrupt.
Matt
[1] https://blog.dan.drown.org/apu2-ntp-server-2/
[2] https://lists.osuosl.org/pipermail/intel-wired-lan/Week-of-Mon-20230130/031970.html
[3] https://noc.as397444.net/ntpgraphs.day/
Hi
If accuracy off of a GPS module is the goal then one needs to start at the module.
All the low cost modules put out their PPS based on an internal free running clock.
It is off from “correct” by some number of NS each time. For historical reasons it
gets called sawtooth error ( = the error chart often looks like a sawtooth).
There are a number of modules that will tell you what the error is in one string
or another. It might have a range of +/- 20 ns. It could be down around +/-2 depending
on the make and model of the unit.
The error is calculated once a second and is provided relative to a pps output.
If you adjust the output rate, working out just what point the “new” error comes
in can be problematic. Most folks just go with 1 pps and move on.
With some care, one can indeed move these edges into a fairly typical PC. Drivers
for this or that are a mixed bag. I’d stick with NTPSec if you want drivers that work.
What typically happens is the pulses are used to come up with an estimate of the
computer’s internal clock. That clock is used to stamp this or that. It’s far more
efficient to do it this way. The data from the external clock is used often enough
to keep the estimate reasonably accurate. Put another way, your timestamp is
always removed from that clock edge by a bit. Faster external clock rates
don’t really do much with this approach.
PTP does this all a bit differently. The above applies to the sorts of programs you
are currently looking at.
Bob
On Feb 1, 2023, at 1:38 PM, John Miller via time-nuts time-nuts@lists.febo.com wrote:
Hi Matt,
This is excellent information, thank you - after reading through all the responses in the thread (wow, this is a wild topic!) and trawling around online a bit, I think that using the SDP pins on the i210 to feed a PPS signal into an x86 PC is what I want to do right now.
I have read Dan Drown's blog post on using the APU2 to achieve this, and while it's more or less exactly what I want to replicate, for now, there are a few gaps I need to fill in - and you may be able to help me do so. I don't have a PC Engines APU2 board yet, but I suspect I'll order one once I have the software side of things ironed out, because I really like their form factor.
What I'm using right now is a Portwell NANO-6050[1], and it has i210 and i218 NICs. The SDP pins on the i210 aren't broken out into nice pads like the APU2 has, but with some magnet wire and a steady hand I was able to connect directly to one of the pins. Where I am struggling right now is ironing out the software configuration side of things. I'm not interested at all in PTP yet, right now the focus is purely on feeding the PPS into chrony via the SDP pins. The GNSS I'm using is a Sparkfun uBlox NEO-M9N GNSS receiver in its default configuration, connected to the computer over USB. PPS pin connected to the i210's SDP0. PPS pulse is 3v3 for 100ms.
I have tried using refclock strings from chrony's examples page[2] as a jumping-off point, but it doesn't make much sense to me. 16Hz PPS with a rate of 16 - why not use 1Hz with a default rate of 1? The Dan Drown blog post makes a little bit more sense, but I think something is missing from the 'relevant chrony.conf' example - notably, it includes a single refclock line with the "pps" option, which according to the chrony.conf docs[4]: "Another time source is needed to complete samples from the refclock." and that example isn't included. Furthermore, his "width" parameter is set to 0.7 milliseconds, which seems tremendously short to me. If the PPS pulses are 100ms (which I understand to be fairly standard) why wouldn't the width be configured as such? I may be misunderstanding this parameter.
Either way, am not able to get chrony to lock up to a PHC refclock.[5] This is what my chrony.conf looks like: https://paste.millerjs.org/ajoxigiquc.txt
I have not been able to use the testptp tool on this system yet - building it on another machine and running the copied-over executable fails, citing too old a version of glibc, and when I try and build it locally it fails for reasons that are unknown to me (I am very much not a C developer). I may have to install a newer OS in order to try this out.
I am going to continue to fiddle with this - I think getting testptp working such that I can verify that I'm actually getting a pulse on SDP0 is the most important thing to confirm right now. I would greatly appreciate any help or feedback!
Thanks,
John
KC1QLN
[1] https://portwell.com/products/detail.php?CUSTCHAR1=NANO-6050
[2] https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic
[3] https://blog.dan.drown.org/apu2-ntp-server-2/
[4] https://chrony.tuxfamily.org/doc/4.3/chrony.conf.html
[5] https://paste.millerjs.org/edebutayoz.txt
On Jan 31, 2023, at 9:43 PM, Matt Corallo timenuts-list@mattcorallo.com wrote:
On 1/30/23 10:15 AM, John Miller via time-nuts wrote:
Hey All,
I'm curious as to what the collective experience is amongst this group when it comes to feeding a timestamp signal into a NIC, either for PTP purposes or for as a normal PPS refclock. The Intel i210 PCIe network card has a few software defined pins that can be used for this purpose, and the chrony documentation has some information about it:
https://chrony.tuxfamily.org/examples.html#_server_using_reference_clock_on_nic
I imagine most of us here use traditional RS232 serial ports to get this signal into an x86 computer, usually using the DCD pin. I've found some implementations of RS232 on PCs don't implement all of the additional signaling pins, so sometimes DCD is flat out missing. In other cases - especially with smaller embedded-type boards only UARTs with Rx/Tx are available to the user. (I'm fiddling with using GPIO pins on a few such systems, but it's quite a struggle.) So, there is a need for getting PPS signals into systems.
There are also highly specialized network interface cards, such as this one: https://www.ebay.com/itm/404117321209
... which does explicitly support PTP timestamping, but it's not clear to me if it could pull in a "standard" PPS signal to be made available to chrony or NTPsec. I haven't found much documentation on the NT20E2 yet, unfortunately, and it may simply not exist for hobbyists.
Does anyone here know if any other network cards that support software defined pins, like the i210 does, or any other methods for getting a PPS signal to be fed into a PC, and of course interpreted correctly?
A friend pointed me at this thread, I just finished hooking up 2 i211s to two separate u-blox receivers to rather good effect. Specifically, I have an APU2 and hooked up the receivers as described at [1]. Note that it doesn't actually matter which of the four pins you hook it up to, any can be configured to interrupt (though you need the patch at [2] for recent kernels).
The serials on the same board come in via a Nuvoton NCT5104D LPC <-> 4xCOM port chip (which I assume is probably not uncommon for many machines these days). The same GPS receivers were hooked up via that via DCD pins, which were properly interrupt'ing but had jitter on the order of 10-25us. Chrony would often report a bit less std dev across a few samples, but the two receivers would wander around the current time and often by off in different directions. With the receivers moved over to the i211s chrony now reports std dev between 5 and 100ns, though given they're always off in the same direction on a similar order of magnitude I think that's the system clock being off more than interrupt latency.
You can find graphs at [3], though excuse the lack of history, I re-soldered a few hours ago and am still testing it so dropping data since last boot.
While the i211 theoretically supports both interrupting for the Software-Defined-Pins and packet timestamping for PTP (and NTP) purposes, it is entirely unclear to me if chrony uses the NIC clock to respond to NTP. chrony happily accepts the hwtimestamping option for the NICs and correctly reads from the NIC's PPS pin as a PHC clock, but there doesn't seem to be any config to hook the two up somehow.
The testptp utility in the kernel source tree tells me that it takes 8000-9000ns to read the NIC's clock, and chrony pretty reliably reports the +/- on a sample from the NIC PPS as +/- 1100-1200ns so it lines up that there's around 1000ns of jitter on the interrupt.
Matt
[1] https://blog.dan.drown.org/apu2-ntp-server-2/
[2] https://lists.osuosl.org/pipermail/intel-wired-lan/Week-of-Mon-20230130/031970.html
[3] https://noc.as397444.net/ntpgraphs.day/
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On 2/1/23 10:38 AM, John Miller via time-nuts wrote:
Hi Matt,
What I'm using right now is a Portwell NANO-6050[1], and it has i210 and i218 NICs. The SDP pins on the i210 aren't broken out into nice pads like the APU2 has, but with some magnet wire and a steady hand I was able to connect directly to one of the pins. Where I am struggling right now is ironing out the software configuration side of things. I'm not interested at all in PTP yet, right now the focus is purely on feeding the PPS into chrony via the SDP pins. The GNSS I'm using is a Sparkfun uBlox NEO-M9N GNSS receiver in its default configuration, connected to the computer over USB. PPS pin connected to the i210's SDP0. PPS pulse is 3v3 for 100ms.
I have tried using refclock strings from chrony's examples page[2] as a jumping-off point, but it doesn't make much sense to me.
16Hz PPS with a rate of 16 - why not use 1Hz with a default rate of 1?
More samples can hide at least some of the noise. As Bob points out in his reply there's a limit,
though, of course, the NEO-M9N datasheet says its time-pulse accuracy is 30ns RMS/60ns 99%. If your
interrupt jitter is less than that, you're not gonna hide much :).
The Dan Drown blog post makes a little bit more sense, but I think something is missing from the 'relevant chrony.conf' example - notably, it includes a single refclock line with the "pps" option, which according to the chrony.conf docs[4]: "Another time source is needed to complete samples from the refclock." and that example isn't included.
A PPS input is just a pulse. chrony has no idea what time that pulse was meant to indicate, only
that it indicated a specific time. You have to somehow hook that pulse up to something else via the
"lock" option. Probably you want to run gpsd and tell chrony about the gpsd input via a "refclock
SHM...noselect" line. There should be examples of how to do this elsewhere
Furthermore, his "width" parameter is set to 0.7 milliseconds, which seems tremendously short to me. If the PPS pulses are 100ms (which I understand to be fairly standard) why wouldn't the width be configured as such? I may be misunderstanding this parameter.
Yea, not sure, that does seem super small. If chrony knows the time (via the lock'ed refclock) with
more accuracy than 0.7/2ms then its fine, but if you're locking to an NMEA input via gpsd you're
gonna have way more variance than that. Ideally your pulse is half the width of your pulse rate, so
500ms if you're doing 1s PPS.
Either way, am not able to get chrony to lock up to a PHC refclock.[5] This is what my chrony.conf looks like: https://paste.millerjs.org/ajoxigiquc.txt
I have not been able to use the testptp tool on this system yet - building it on another machine and running the copied-over executable fails, citing too old a version of glibc, and when I try and build it locally it fails for reasons that are unknown to me (I am very much not a C developer). I may have to install a newer OS in order to try this out.
I am going to continue to fiddle with this - I think getting testptp working such that I can verify that I'm actually getting a pulse on SDP0 is the most important thing to confirm right now. I would greatly appreciate any help or feedback!
chrony has been a bit...fidgety with me, the testptp utility will show at least whether your input
is pulsing and being read or not.
Matt