Discussion and technical support related to USRP, UHD, RFNoC
View all threadsDear Sir or Madam,
Our group is trying to program some signal processing function onto the FPGA of the USRP B210 board. We have already install the Xilinx ISE 14.7 software, but a problem occurred when we build the FPGA system on Ubuntu system.
When I was trying to run: make B210 in the directory of /UHD installation directory/uhd/fpga-src/usrp3/top/b200, I got the following error messages:
/b200$ sudo make B210
/bin/sh: 1: xtclsh: not found
ISE Version:
make -f Makefile.b200.inc bin NAME=B210 DEVICE=XC6SLX150 EXTRA_DEFS="TARGET_B210=1 "
/bin/sh: 1: xtclsh: not found
make[1]: Entering directory /home/arondightxia/gnusrc/uhd/fpga-src/usrp3/top/b200' make[1]: *** No rule to make target build-B210//b200.bit', needed by bin'. Stop. make[1]: Leaving directory /home/arondightxia/gnusrc/uhd/fpga-src/usrp3/top/b200'
make: *** [B210] Error 2
I am sure that I did run source /home/Xilinx/14.7/ISE_DS/settings64.sh, and I tried to run git status under the directory /home/arondightxia/gnusrc/uhd/fpga-src/, as suggested in
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-February/012574.html
Then I get the following message:
HEAD detached at c98fc3b
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git checkout -- <file>..." to discard changes in working directory)
modified: top/b200/coregen/coregen.cgp
modified: top/b200/coregen_dsp/coregen.cgp
no changes added to commit (use "git add" and/or "git commit -a")
However, I do not sure what should be done to fix the error. Do you have any idea how to solve this issues? I will really appreciate it if you can give me some suggestion.
Thank you very much.
Sincerely,
Hongtao Xia
You must source the settings* script from the Xilinx bin/ directory, as
explained in
http://files.ettus.com/manual/md_usrp3_build_instructions.html
Best regards,
Marcus
On 11/17/2015 02:35 AM, Xia, Hongtao via USRP-users wrote:
Dear Sir or Madam,
Our group is trying to program some signal processing function onto
the FPGA of the USRP B210 board. We have already install the Xilinx
ISE 14.7 software, but a problem occurred when we build the FPGA
system on Ubuntu system.
When I was trying to run: make B210 in the directory of /UHD
installation directory/uhd/fpga-src/usrp3/top/b200, I got the
following error messages:
/b200$ sudo make B210
/bin/sh: 1: xtclsh: not found
ISE Version:
make -f Makefile.b200.inc bin NAME=B210 DEVICE=XC6SLX150
EXTRA_DEFS="TARGET_B210=1 "
/bin/sh: 1: xtclsh: not found
make[1]: Entering directory
/home/arondightxia/gnusrc/uhd/fpga-src/usrp3/top/b200' make[1]: *** No rule to make target build-B210//b200.bit', needed by
bin'. Stop. make[1]: Leaving directory /home/arondightxia/gnusrc/uhd/fpga-src/usrp3/top/b200'
make: *** [B210] Error 2
I am sure that I did run source
/home/Xilinx/14.7/ISE_DS/settings64.sh, and I tried to run git status
under the directory /home/arondightxia/gnusrc/uhd/fpga-src/, as
suggested in
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-February/012574.html
Then I get the following message:
HEAD detached at c98fc3b
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git checkout -- <file>..." to discard changes in working
directory)
modified: top/b200/coregen/coregen.cgp
modified: top/b200/coregen_dsp/coregen.cgp
no changes added to commit (use "git add" and/or "git commit -a")
However, I do not sure what should be done to fix the error. Do you
have any idea how to solve this issues? I will really appreciate it if
you can give me some suggestion.
Thank you very much.
Sincerely,
Hongtao Xia
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
On 16.11.2015 17:35, Xia, Hongtao via USRP-users wrote:
/b200$ sudo make B210
Have you tried without 'sudo'?
M