Hello Everyone, Today, we are officially releasing support for the Xilinx Vivado FPGA Design Suite. All USRP products with FPGAs that can be targeted by Vivado will have full build support using the Ettus Research FPGA tool-chain. This includes support for the USRP X300, USRP X310 and USRP E310. Please note that the USRP B-Series, USRP N-series and the USRP E1x0 products are unaffected by this change and will continue to use Xilinx ISE. *Benefits and New Features* - The Vivado Design Suite achieves high device utilization because it employs advanced fitting algorithms and allows very high density designs - Vivado has superior memory utilization and runtime performance. Build times for typical USRP designs have improved by about 30-40% - IP Integration is easier and much more streamlined. - In addition to the tool change, we have made significant improvements to the X3x0 and E310 designs. High speed IO interfaces are more robust to temperature and process variations. Timing closure is easier to attain for full/borderline designs. - FPGA images built with Vivado are fully compatible with UHD, GnuRadio and NI-USRP with LabVIEW - There have been multiple usability enhancements in the USRP FPGA build system. This update has been made in the master branch in the uhd and fpga repositories: https://github.com/EttusResearch/uhd/tree/master https://github.com/EttusResearch/fpga/tree/master *How does this affect you?* - Users using pre-built FPGA images with UHD are *not* affected by this change. You can simply pull the latest UHD master, run the installed uhd_images_downloader and you will automatically get the Vivado images. - Users that are simply building *FPGA* master without any code changes will just need to install Xilinx Vivado. The new build system is mostly similar to the one for Xilinx ISE. You can navigate to the top level product directory and just run make <target> to build an FPGA image. Detailed build instructions can be found here: *https://github.com/EttusResearch/fpga/blob/master/docs/usrp3/build_instructions.md <https://github.com/EttusResearch/fpga/blob/master/docs/usrp3/build_instructions.md>* - This change will affect all users that are currently building FPGA source from master and have HDL customization. If your code is just interacting with components of the Ettus design, you will see the benefits of Vivado without much porting. If you are using Xilinx provided IP, you may need to re-target it for Vivado. The Vivado Design Suite is recommended by Xilinx for all 7-series FPGAs and is a vast improvement over ISE, however, it is significantly different from ISE so we recommend that any FPGA customization be re-validated before deployment. *Migration and Support Plan* - This update only affects master which is considered 'unstable'. If you want to run stable code, we recommend using the maint branch which still has legacy support for Xilinx ISE. - For the next UHD minor release (3.9.0), master and maint will become one and we will officially drop Xilinx ISE support for all products that are supported by Vivado (i.e. USRP X3x0, E310). This legacy support window is tentatively about 3 months. - All bugfixes from maint will carry forward to master as usual. However, during the legacy support period, we will back-port only critical bugfixes from master into maint. All new development will be focused on Vivado. Let us know if you have any feedback. More features and products are coming up! Cheers, *Ashish Chaudhari* | Senior Software Engineer | High Frequency Measurements - RF Ettus Research, *A National Instruments Company* ashish.chaudhari@ettus.com

W dniu 01.05.2015 o 21:55, Ashish Chaudhari via USRP-users pisze: > Hello Everyone, > > Today, we are officially releasing support for the Xilinx Vivado FPGA > Design Suite. All USRP products with FPGAs that can be targeted by > Vivado will have full build support using the Ettus Research FPGA > tool-chain. This includes support for the USRP X300, USRP X310 and > USRP E310. Please note that the USRP B-Series, USRP N-series and the > USRP E1x0 products are unaffected by this change and will continue to > use Xilinx ISE. > > *Benefits and New Features* > - The Vivado Design Suite achieves high device utilization because it > employs advanced fitting algorithms and allows very high density designs > - Vivado has superior memory utilization and runtime performance. > Build times for typical USRP designs have improved by about 30-40% > - IP Integration is easier and much more streamlined. > - In addition to the tool change, we have made significant > improvements to the X3x0 and E310 designs. High speed IO interfaces > are more robust to temperature and process variations. Timing closure > is easier to attain for full/borderline designs. > - FPGA images built with Vivado are fully compatible with UHD, > GnuRadio and NI-USRP with LabVIEW > - There have been multiple usability enhancements in the USRP FPGA > build system. > > This update has been made in the master branch in the uhd and fpga > repositories: > https://github.com/EttusResearch/uhd/tree/master > https://github.com/EttusResearch/fpga/tree/master > > *How does this affect you?* > - Users using pre-built FPGA images with UHD are *not* affected by > this change. You can simply pull the latest UHD master, run the > installed uhd_images_downloader and you will automatically get the > Vivado images. > - Users that are simply building *FPGA* master without any code > changes will just need to install Xilinx Vivado. The new build system > is mostly similar to the one for Xilinx ISE. You can navigate to the > top level product directory and just run make <target> to build an > FPGA image. Detailed build instructions can be found > here: _https://github.com/EttusResearch/fpga/blob/master/docs/usrp3/build_instructions.md_ > - This change will affect all users that are currently building FPGA > source from master and have HDL customization. If your code is just > interacting with components of the Ettus design, you will see the > benefits of Vivado without much porting. If you are using Xilinx > provided IP, you may need to re-target it for Vivado. The Vivado > Design Suite is recommended by Xilinx for all 7-series FPGAs and is a > vast improvement over ISE, however, it is significantly different from > ISE so we recommend that any FPGA customization be re-validated before > deployment. > > *Migration and Support Plan* > - This update only affects master which is considered 'unstable'. If > you want to run stable code, we recommend using the maint branch which > still has legacy support for Xilinx ISE. > - For the next UHD minor release (3.9.0), master and maint will become > one and we will officially drop Xilinx ISE support for all products > that are supported by Vivado (i.e. USRP X3x0, E310). This legacy > support window is tentatively about 3 months. > - All bugfixes from maint will carry forward to master as usual. > However, during the legacy support period, we will back-port only > critical bugfixes from master into maint. All new development will be > focused on Vivado. > > Let us know if you have any feedback. More features and products are > coming up! > > Cheers, > > *Ashish Chaudhari* | Senior Software Engineer | High Frequency > Measurements - RF > Ettus Research, /A National Instruments Company/ > ashish.chaudhari@ettus.com <mailto:ashish.chaudhari@ettus.com> > > Hi, Should Vivado also work with rfnoc-devel branch? I have issues with generating binaries for USRP X300/X310 from rfnoc-devel branch with Vivado v2015.1. Everything works fine with ISE. Best Regards, Piotr Krysik

Hi Piotr, I am actively working on rfnoc-devel to use Vivado. I'll make an announcement once it is complete. Jonathon On Mon, May 4, 2015 at 6:35 AM, Piotr Krysik via USRP-users <usrp-users@lists.ettus.com> wrote: > W dniu 01.05.2015 o 21:55, Ashish Chaudhari via USRP-users pisze: >> Hello Everyone, >> >> Today, we are officially releasing support for the Xilinx Vivado FPGA >> Design Suite. All USRP products with FPGAs that can be targeted by >> Vivado will have full build support using the Ettus Research FPGA >> tool-chain. This includes support for the USRP X300, USRP X310 and >> USRP E310. Please note that the USRP B-Series, USRP N-series and the >> USRP E1x0 products are unaffected by this change and will continue to >> use Xilinx ISE. >> >> *Benefits and New Features* >> - The Vivado Design Suite achieves high device utilization because it >> employs advanced fitting algorithms and allows very high density designs >> - Vivado has superior memory utilization and runtime performance. >> Build times for typical USRP designs have improved by about 30-40% >> - IP Integration is easier and much more streamlined. >> - In addition to the tool change, we have made significant >> improvements to the X3x0 and E310 designs. High speed IO interfaces >> are more robust to temperature and process variations. Timing closure >> is easier to attain for full/borderline designs. >> - FPGA images built with Vivado are fully compatible with UHD, >> GnuRadio and NI-USRP with LabVIEW >> - There have been multiple usability enhancements in the USRP FPGA >> build system. >> >> This update has been made in the master branch in the uhd and fpga >> repositories: >> https://github.com/EttusResearch/uhd/tree/master >> https://github.com/EttusResearch/fpga/tree/master >> >> *How does this affect you?* >> - Users using pre-built FPGA images with UHD are *not* affected by >> this change. You can simply pull the latest UHD master, run the >> installed uhd_images_downloader and you will automatically get the >> Vivado images. >> - Users that are simply building *FPGA* master without any code >> changes will just need to install Xilinx Vivado. The new build system >> is mostly similar to the one for Xilinx ISE. You can navigate to the >> top level product directory and just run make <target> to build an >> FPGA image. Detailed build instructions can be found >> here: _https://github.com/EttusResearch/fpga/blob/master/docs/usrp3/build_instructions.md_ >> - This change will affect all users that are currently building FPGA >> source from master and have HDL customization. If your code is just >> interacting with components of the Ettus design, you will see the >> benefits of Vivado without much porting. If you are using Xilinx >> provided IP, you may need to re-target it for Vivado. The Vivado >> Design Suite is recommended by Xilinx for all 7-series FPGAs and is a >> vast improvement over ISE, however, it is significantly different from >> ISE so we recommend that any FPGA customization be re-validated before >> deployment. >> >> *Migration and Support Plan* >> - This update only affects master which is considered 'unstable'. If >> you want to run stable code, we recommend using the maint branch which >> still has legacy support for Xilinx ISE. >> - For the next UHD minor release (3.9.0), master and maint will become >> one and we will officially drop Xilinx ISE support for all products >> that are supported by Vivado (i.e. USRP X3x0, E310). This legacy >> support window is tentatively about 3 months. >> - All bugfixes from maint will carry forward to master as usual. >> However, during the legacy support period, we will back-port only >> critical bugfixes from master into maint. All new development will be >> focused on Vivado. >> >> Let us know if you have any feedback. More features and products are >> coming up! >> >> Cheers, >> >> *Ashish Chaudhari* | Senior Software Engineer | High Frequency >> Measurements - RF >> Ettus Research, /A National Instruments Company/ >> ashish.chaudhari@ettus.com <mailto:ashish.chaudhari@ettus.com> >> >> > Hi, > > Should Vivado also work with rfnoc-devel branch? I have issues with > generating binaries for USRP X300/X310 from rfnoc-devel branch with > Vivado v2015.1. > > Everything works fine with ISE. > > Best Regards, > Piotr Krysik > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com