Re: [time-nuts] Frequency Stability Analyzer - ZCDs
Was considering 16 LVDS receivers and IDELAYS to emulate a single fast
comparator,
I haven't done serious work with FPGAs in 10 or 15 years.
That seems like an obvious hack, but it depends on the implementation details
inside the FPGA. What's the granularity? How much does it change from chip
to chip or over voltage and temperature?
Has anybody published any data?
Another possibility is to use trace delays on the PCB. You have a lumped
delay line with capacitance from the input pad. This may not be practical for
short delays where the bond wires on the chip are not short relative to the
trace lengths.
--
These are my opinions. I hate spam.
Hi
there is quite a bit done in this area of FPGAs, IDELAYS etc for this
application. and also quite a bit written already on TIMENUTS I find
from archives.
From my POV, the pressure on the design is the input circuitry...My gut
is to start with a ADCMP572 and drive several FPGA pins with PECL or
CML . BUT ! I have not thought about the problem very much, nor do I
have much experience with this application (and trying to be a little
modest here considering the company I am in) . The temperature
variability of the comparator hysteresis might be some issue with the
comparator.
I think the FPGA method certainly has many limits , compared to the
analog methods (dual slope phase comparators driving 24 bit ADCs etc,
vernier methods.) But my intuition is that a design that can leverage a
hybrid of analog methods and some handy features available in modern
FPGAs can get the performance.
The idea is, to produce a general purpose high performance measurement
platform for HF region clocks, and pps, without having to resort to
buying an SR620.. analog front end, FPGA (VHDL) , drive for a standard
HD44780 LCD controller to display stuff, and output (USB most likely)
for data analysis on a platform that has plenty of storage.
IDELAYS - there is good granuality (26ps Artix -1) (3 ps Ultrascale
Kintex) , temperature stability is a bit average but that can be dealt
with. The IO delays are variable on the fly for some architectures. It
is not the whole story, but one of the bullets in the revolver in
acheiving the desired granuarity. There are several calibration options.
jitter added in the routing can be minimize with some manual placement
strategies
There is an additional handle at the place and route level on
specifying constraint delays. This is pretty rough but if a good
calibration strategy can be developed, it is worthwhile. (IE conformance
to the constraint delays may vary from build to build so there needs to
be a bit of manual placement ) .
Yes, I think trace delays are useful, although rise time of the
devices together with PCB bandwidth muddies the water , and hence
uncertainty etc etc
I'd like to use a Lattice MACH X02 for this job but I think I will use a
Xilinx due to my familiarity with them (and indeed, performance and
control of the synthesis tools) , and the speed.
(i'm actually an RF person but FPGAs and DSP is an essential these
days) .
-glen
On 27/07/2019 11:49 AM, Hal Murray wrote:
Was considering 16 LVDS receivers and IDELAYS to emulate a single fast
comparator,
I haven't done serious work with FPGAs in 10 or 15 years.
That seems like an obvious hack, but it depends on the implementation details
inside the FPGA. What's the granularity? How much does it change from chip
to chip or over voltage and temperature?
Has anybody published any data?
Another possibility is to use trace delays on the PCB. You have a lumped
delay line with capacitance from the input pad. This may not be practical for
short delays where the bond wires on the chip are not short relative to the
trace lengths.
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
CERN amongst others use it. The pin programmable filtering allows its bandwidth to be optimised to suit the input signal frequency and amplitude. This could be user selectable via front panel controls or under computer control.
Comparators are almost always noisier.
Oliver Collins wrote a paper on optimising such sine to square converters.
I extended the analysis to allow optimisation when the input noise of the cascaded stages arent equal.
Bruce
On 27 July 2019 at 16:26 Glen English VK1XX glenlist@pacificmedia.com.au wrote:
Hi
there is quite a bit done in this area of FPGAs, IDELAYS etc for this
application. and also quite a bit written already on TIMENUTS I find
from archives.
From my POV, the pressure on the design is the input circuitry...My gut
is to start with a ADCMP572 and drive several FPGA pins with PECL or
CML . BUT ! I have not thought about the problem very much, nor do I
have much experience with this application (and trying to be a little
modest here considering the company I am in) . The temperature
variability of the comparator hysteresis might be some issue with the
comparator.
I think the FPGA method certainly has many limits , compared to the
analog methods (dual slope phase comparators driving 24 bit ADCs etc,
vernier methods.) But my intuition is that a design that can leverage a
hybrid of analog methods and some handy features available in modern
FPGAs can get the performance.
The idea is, to produce a general purpose high performance measurement
platform for HF region clocks, and pps, without having to resort to
buying an SR620.. analog front end, FPGA (VHDL) , drive for a standard
HD44780 LCD controller to display stuff, and output (USB most likely)
for data analysis on a platform that has plenty of storage.
IDELAYS - there is good granuality (26ps Artix -1) (3 ps Ultrascale
Kintex) , temperature stability is a bit average but that can be dealt
with. The IO delays are variable on the fly for some architectures. It
is not the whole story, but one of the bullets in the revolver in
acheiving the desired granuarity. There are several calibration options.
jitter added in the routing can be minimize with some manual placement
strategies
There is an additional handle at the place and route level on
specifying constraint delays. This is pretty rough but if a good
calibration strategy can be developed, it is worthwhile. (IE conformance
to the constraint delays may vary from build to build so there needs to
be a bit of manual placement ) .
Yes, I think trace delays are useful, although rise time of the
devices together with PCB bandwidth muddies the water , and hence
uncertainty etc etc
I'd like to use a Lattice MACH X02 for this job but I think I will use a
Xilinx due to my familiarity with them (and indeed, performance and
control of the synthesis tools) , and the speed.
(i'm actually an RF person but FPGAs and DSP is an essential these
days) .
-glen
On 27/07/2019 11:49 AM, Hal Murray wrote:
Was considering 16 LVDS receivers and IDELAYS to emulate a single fast
comparator,
I haven't done serious work with FPGAs in 10 or 15 years.
That seems like an obvious hack, but it depends on the implementation details
inside the FPGA. What's the granularity? How much does it change from chip
to chip or over voltage and temperature?
Has anybody published any data?
Another possibility is to use trace delays on the PCB. You have a lumped
delay line with capacitance from the input pad. This may not be practical for
short delays where the bond wires on the chip are not short relative to the
trace lengths.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
In all our critical work we use the LTC6957,we call it the Bruce circuit, only problem at 78 and 80 difficult to solder
Bert Kehren
In a message dated 7/27/2019 4:04:50 AM Eastern Standard Time, bruce.griffiths@xtra.co.nz writes:
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
CERN amongst others use it. The pin programmable filtering allows its bandwidth to be optimised to suit the input signal frequency and amplitude. This could be user selectable via front panel controls or under computer control.
Comparators are almost always noisier.
Oliver Collins wrote a paper on optimising such sine to square converters.
I extended the analysis to allow optimisation when the input noise of the cascaded stages arent equal.
Bruce
On 27 July 2019 at 16:26 Glen English VK1XX glenlist@pacificmedia.com.au wrote:
Hi
there is quite a bit done in this area of FPGAs, IDELAYS etc for this
application. and also quite a bit written already on TIMENUTS I find
from archives.
From my POV, the pressure on the design is the input circuitry...My gut
is to start with a ADCMP572 and drive several FPGA pins with PECL or
CML . BUT ! I have not thought about the problem very much, nor do I
have much experience with this application (and trying to be a little
modest here considering the company I am in) . The temperature
variability of the comparator hysteresis might be some issue with the
comparator.
I think the FPGA method certainly has many limits , compared to the
analog methods (dual slope phase comparators driving 24 bit ADCs etc,
vernier methods.) But my intuition is that a design that can leverage a
hybrid of analog methods and some handy features available in modern
FPGAs can get the performance.
The idea is, to produce a general purpose high performance measurement
platform for HF region clocks, and pps, without having to resort to
buying an SR620.. analog front end, FPGA (VHDL) , drive for a standard
HD44780 LCD controller to display stuff, and output (USB most likely)
for data analysis on a platform that has plenty of storage.
IDELAYS - there is good granuality (26ps Artix -1) (3 ps Ultrascale
Kintex) , temperature stability is a bit average but that can be dealt
with. The IO delays are variable on the fly for some architectures. It
is not the whole story, but one of the bullets in the revolver in
acheiving the desired granuarity. There are several calibration options.
jitter added in the routing can be minimize with some manual placement
strategies
There is an additional handle at the place and route level on
specifying constraint delays. This is pretty rough but if a good
calibration strategy can be developed, it is worthwhile. (IE conformance
to the constraint delays may vary from build to build so there needs to
be a bit of manual placement ) .
Yes, I think trace delays are useful, although rise time of the
devices together with PCB bandwidth muddies the water , and hence
uncertainty etc etc
I'd like to use a Lattice MACH X02 for this job but I think I will use a
Xilinx due to my familiarity with them (and indeed, performance and
control of the synthesis tools) , and the speed.
(i'm actually an RF person but FPGAs and DSP is an essential these
days) .
-glen
On 27/07/2019 11:49 AM, Hal Murray wrote:
Was considering 16 LVDS receivers and IDELAYS to emulate a single fast
comparator,
I haven't done serious work with FPGAs in 10 or 15 years.
That seems like an obvious hack, but it depends on the implementation details
inside the FPGA. What's the granularity? How much does it change from chip
to chip or over voltage and temperature?
Has anybody published any data?
Another possibility is to use trace delays on the PCB. You have a lumped
delay line with capacitance from the input pad. This may not be practical for
short delays where the bond wires on the chip are not short relative to the
trace lengths.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
On Sat, 27 Jul 2019 18:21:50 +1200 (NZST)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
If you want to have a single component ZCD, then I agree.
Otherwise, a multi-stage Collins like ZCD can perform better.
Especially, if the input waveform has known properties, then
the multi-stage approach can properly optimize for those.
Comparators are almost always noisier.
Oliver Collins wrote a paper on optimising such sine to square converters.
I extended the analysis to allow optimisation when the input noise of the
cascaded stages arent equal.
There is one important point with Collins' analysis that hardly gets
mentioned: His analysis assumes that the output signal of a stage is
trapezoid. While this is true for high gain settings, it is not for
low gain settings. Ie in his example with 6 stages, the first three stages
have a total gain of 23, ie the signal has still significant curvature.
Thus Collins' analysis the noise contribution of these three stages contains
significant erros. See the attached paper for details.
Additionally, in a multi-stage ZCD, it is very important to keep the
duty cycle at 50%, as otherwise the even harmonics give rise to an increase
of flicker noise due to noise up- and down-conversion. See [1] for details.
Attila Kinali
[1] "A Physical Sine-to-Square Converter Noise Model", by Attila Kinali. 2018.
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes
Hi,
On 2019-07-27 12:07, Attila Kinali wrote:
On Sat, 27 Jul 2019 18:21:50 +1200 (NZST)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
If you want to have a single component ZCD, then I agree.
Otherwise, a multi-stage Collins like ZCD can perform better.
Especially, if the input waveform has known properties, then
the multi-stage approach can properly optimize for those.
The LTC6957 is a multi-stage device with only 4 different bandwidths to
optimize for, so you can do better. It may however be good enough for
many purposes.
Comparators are almost always noisier.
Oliver Collins wrote a paper on optimising such sine to square converters.
I extended the analysis to allow optimisation when the input noise of the
cascaded stages arent equal.
There is one important point with Collins' analysis that hardly gets
mentioned: His analysis assumes that the output signal of a stage is
trapezoid. While this is true for high gain settings, it is not for
low gain settings. Ie in his example with 6 stages, the first three stages
have a total gain of 23, ie the signal has still significant curvature.
Thus Collins' analysis the noise contribution of these three stages contains
significant erros. See the attached paper for details.
The trapetzoid model is a simplification which is better than sine or
square, but not perfect.
Another thing with Bruce noticed was that it assumed the same noise from
all op-amps, but you can choose different op-amps with different noise
and slope-rates and then you need different formulas, which Bruce produced.
Additionally, in a multi-stage ZCD, it is very important to keep the
duty cycle at 50%, as otherwise the even harmonics give rise to an increase
of flicker noise due to noise up- and down-conversion. See [1] for details.
This effect has been seen by NIST for dividers, which made them conclude
one needs to end with a divide by 2.
Cheers,
Magnus
Attila Kinali
[1] "A Physical Sine-to-Square Converter Noise Model", by Attila Kinali. 2018.
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
Hi
Assuming we are still talking about a test instrument that needs to handle a variety of levels
and a range of frequencies, the 6957 is probably as good as anything.
With a “full up” Collins style circuit, you very much need to optimize for a specific input.
Change that and you change the circuit. 1 MHz, 10 MHz, and 100 MHz will each “want”
a very different set of parts. Change levels 10:1 and that has an impact ….
Even if you do get a circuit up and running, take a look at the TC of the caps in all those
filter stages. Matching all that up for a valid test is going to be a bit hard. You have a wide
range of values and (likely) a range of capacitor types. Not an easy problem to solve without
ovenizing the whole beast. Do that and you no longer have a “simple” box … (and no guarantee
a basic oven will solve the problem …)
Bob
On Jul 27, 2019, at 6:32 AM, Magnus Danielson magnus@rubidium.se wrote:
Hi,
On 2019-07-27 12:07, Attila Kinali wrote:
On Sat, 27 Jul 2019 18:21:50 +1200 (NZST)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
If you want to have a single component ZCD, then I agree.
Otherwise, a multi-stage Collins like ZCD can perform better.
Especially, if the input waveform has known properties, then
the multi-stage approach can properly optimize for those.
The LTC6957 is a multi-stage device with only 4 different bandwidths to
optimize for, so you can do better. It may however be good enough for
many purposes.
Comparators are almost always noisier.
Oliver Collins wrote a paper on optimising such sine to square converters.
I extended the analysis to allow optimisation when the input noise of the
cascaded stages arent equal.
There is one important point with Collins' analysis that hardly gets
mentioned: His analysis assumes that the output signal of a stage is
trapezoid. While this is true for high gain settings, it is not for
low gain settings. Ie in his example with 6 stages, the first three stages
have a total gain of 23, ie the signal has still significant curvature.
Thus Collins' analysis the noise contribution of these three stages contains
significant erros. See the attached paper for details.
The trapetzoid model is a simplification which is better than sine or
square, but not perfect.
Another thing with Bruce noticed was that it assumed the same noise from
all op-amps, but you can choose different op-amps with different noise
and slope-rates and then you need different formulas, which Bruce produced.
Additionally, in a multi-stage ZCD, it is very important to keep the
duty cycle at 50%, as otherwise the even harmonics give rise to an increase
of flicker noise due to noise up- and down-conversion. See [1] for details.
This effect has been seen by NIST for dividers, which made them conclude
one needs to end with a divide by 2.
Cheers,
Magnus
Attila Kinali
[1] "A Physical Sine-to-Square Converter Noise Model", by Attila Kinali. 2018.
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
Hi,
Yes, indeed, so for many purposes the 6957 is probably good enough, and
actually better than many classical approaches (i.e. direct
comparators). It is when you design for a fixed or very narrow range of
frequencies that you should consider rolling your own, assuming the
performance of the 6957 becomes a limit to what you can achieve.
Cheers,
Magnus
On 2019-07-27 15:49, Bob kb8tq wrote:
Hi
Assuming we are still talking about a test instrument that needs to handle a variety of levels
and a range of frequencies, the 6957 is probably as good as anything.
With a “full up” Collins style circuit, you very much need to optimize for a specific input.
Change that and you change the circuit. 1 MHz, 10 MHz, and 100 MHz will each “want”
a very different set of parts. Change levels 10:1 and that has an impact ….
Even if you do get a circuit up and running, take a look at the TC of the caps in all those
filter stages. Matching all that up for a valid test is going to be a bit hard. You have a wide
range of values and (likely) a range of capacitor types. Not an easy problem to solve without
ovenizing the whole beast. Do that and you no longer have a “simple” box … (and no guarantee
a basic oven will solve the problem …)
Bob
On Jul 27, 2019, at 6:32 AM, Magnus Danielson magnus@rubidium.se wrote:
Hi,
On 2019-07-27 12:07, Attila Kinali wrote:
On Sat, 27 Jul 2019 18:21:50 +1200 (NZST)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
If you want to have a single component ZCD, then I agree.
Otherwise, a multi-stage Collins like ZCD can perform better.
Especially, if the input waveform has known properties, then
the multi-stage approach can properly optimize for those.
The LTC6957 is a multi-stage device with only 4 different bandwidths to
optimize for, so you can do better. It may however be good enough for
many purposes.
Comparators are almost always noisier.
Oliver Collins wrote a paper on optimising such sine to square converters.
I extended the analysis to allow optimisation when the input noise of the
cascaded stages arent equal.
There is one important point with Collins' analysis that hardly gets
mentioned: His analysis assumes that the output signal of a stage is
trapezoid. While this is true for high gain settings, it is not for
low gain settings. Ie in his example with 6 stages, the first three stages
have a total gain of 23, ie the signal has still significant curvature.
Thus Collins' analysis the noise contribution of these three stages contains
significant erros. See the attached paper for details.
The trapetzoid model is a simplification which is better than sine or
square, but not perfect.
Another thing with Bruce noticed was that it assumed the same noise from
all op-amps, but you can choose different op-amps with different noise
and slope-rates and then you need different formulas, which Bruce produced.
Additionally, in a multi-stage ZCD, it is very important to keep the
duty cycle at 50%, as otherwise the even harmonics give rise to an increase
of flicker noise due to noise up- and down-conversion. See [1] for details.
This effect has been seen by NIST for dividers, which made them conclude
one needs to end with a divide by 2.
Cheers,
Magnus
Attila Kinali
[1] "A Physical Sine-to-Square Converter Noise Model", by Attila Kinali. 2018.
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
well. thank you everyone for your contributions !
I had a good night in reading the references.
I agree the cascaded band-limited limiter strategy is eminently suitable.
That LT part looks like an excellent option, of course,
horses-for-courses caveat applies for freqs and risetimes...
On comparators. Much of the 'noisyness' of comparators comes from the
the use of a super wideband comparator say 5GHz, the noise in even a 50
ohm termination at room temperature is a few tens of microvolts and adds
a fair bit of noise. I've dealt with this up to 500 MHz by filtering
before comparison, but tricky for GHz ops...
-glen
On 28/07/2019 1:03 AM, Magnus Danielson wrote:
Hi,
Yes, indeed, so for many purposes the 6957 is probably good enough, and
actually better than many classical approaches (i.e. direct
comparators). It is when you design for a fixed or very narrow range of
frequencies that you should consider rolling your own, assuming the
performance of the 6957 becomes a limit to what you can achieve.
Cheers,
Magnus
On 2019-07-27 15:49, Bob kb8tq wrote:
Hi
Assuming we are still talking about a test instrument that needs to handle a variety of levels
and a range of frequencies, the 6957 is probably as good as anything.
With a “full up” Collins style circuit, you very much need to optimize for a specific input.
Change that and you change the circuit. 1 MHz, 10 MHz, and 100 MHz will each “want”
a very different set of parts. Change levels 10:1 and that has an impact ….
Even if you do get a circuit up and running, take a look at the TC of the caps in all those
filter stages. Matching all that up for a valid test is going to be a bit hard. You have a wide
range of values and (likely) a range of capacitor types. Not an easy problem to solve without
ovenizing the whole beast. Do that and you no longer have a “simple” box … (and no guarantee
a basic oven will solve the problem …)
Bob
On Jul 27, 2019, at 6:32 AM, Magnus Danielson magnus@rubidium.se wrote:
Hi,
On 2019-07-27 12:07, Attila Kinali wrote:
On Sat, 27 Jul 2019 18:21:50 +1200 (NZST)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
The LTC6957 is a better choice for squaring up sinewaves:
http://www.ko4bb.com/getsimple/index.php?id=phase-noise-and-other-measurements-with-a-timepod
If you want to have a single component ZCD, then I agree.
Otherwise, a multi-stage Collins like ZCD can perform better.
Especially, if the input waveform has known properties, then
the multi-stage approach can properly optimize for those.
The LTC6957 is a multi-stage device with only 4 different bandwidths to
optimize for, so you can do better. It may however be good enough for
many purposes.
Comparators are almost always noisier.
Oliver Collins wrote a paper on optimising such sine to square converters.
I extended the analysis to allow optimisation when the input noise of the
cascaded stages arent equal.
There is one important point with Collins' analysis that hardly gets
mentioned: His analysis assumes that the output signal of a stage is
trapezoid. While this is true for high gain settings, it is not for
low gain settings. Ie in his example with 6 stages, the first three stages
have a total gain of 23, ie the signal has still significant curvature.
Thus Collins' analysis the noise contribution of these three stages contains
significant erros. See the attached paper for details.
The trapetzoid model is a simplification which is better than sine or
square, but not perfect.
Another thing with Bruce noticed was that it assumed the same noise from
all op-amps, but you can choose different op-amps with different noise
and slope-rates and then you need different formulas, which Bruce produced.
Additionally, in a multi-stage ZCD, it is very important to keep the
duty cycle at 50%, as otherwise the even harmonics give rise to an increase
of flicker noise due to noise up- and down-conversion. See [1] for details.
This effect has been seen by NIST for dividers, which made them conclude
one needs to end with a divide by 2.
Cheers,
Magnus
Attila Kinali
[1] "A Physical Sine-to-Square Converter Noise Model", by Attila Kinali. 2018.
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
OK research people...since this forum is loaded with bleeding edge
understanding, Is there such a thing in the lab as a material that can
store, in a 2 level (1 bit) format (or more) , a discrete time
representation of some event ?
In my simple example (dream), an arrangement of some molecular or some
quantum storage medium, that can store an event at discrete intervals of
say, 100fs ? That is, the duration of the storage might be 1nS, storing
the state of something, at 100fs intervals (example ) ....having a (for
example) sample storage of 10000 samples, and the ability to freeze that
event (in some atomic level memory) for later readout once only or
continuously looped ?
No, I am not proposing this for my period /frequency analyser, I was
just wondering about super high speed digitization and storage of very
fast very short events.
-glen