sysclock source for AD9912 DDS?
On 12/31/13 8:07 AM, Anders Wallin wrote:
Could the remaining -60 dBc spurs at +/- 50 kHz be due to my 10MHz clock
source, an Agilent 33120A?
Yes the spurs could be from your source. that's a function generator/ARB
and spectral purity isn't one of the big design criteria for that kind
of device.
The spec sheet says spurious non-harmonic signals are supposed to be
down -65dBc + 6dB/octave above 1 MHz.
http://cp.literature.agilent.com/litweb/pdf/5968-0125EN.pdf
I don't know all the gory details of how the 33120 works inside (though
I've got 3 or 4 of them in my lab at work), but in general, it has a DDS
running at 40MHz that clocks samples out of a waveform table to a 12 bit
DAC. The output from the DAC is run through some analog circuitry for
doing AM and setting offsets and levels.
http://cp.literature.agilent.com/litweb/pdf/33120-90017.pdf
50 kHz is somewhat suspicious.. do you have any switching power supplies
at that rate around? It doesn't take much noise added to a sine wave
running into a comparator to create spurs. I've had that problem with
leakage of a 66MHz processor clock into a 50 MHz sampling clock.
Hej Anders,
On 31/12/13 08:31, Anders Wallin wrote:
Thanks for all replies so far!
It looks like I will play around with the evaluation board some more, and
see if I can get the on-chip PLL to behave better.
The settings with 2x edge-detector and 60x PLL were the only ones I could
find where the output frequency setting in the software corresponded to the
actual output frequency - hence I tested only with 10MHz x120 = 1200 MHz
sysclock. I have asked about this on the AD forum, but no replies yet.
If that doesn't work the suggested ADF4351 (or similar) evaluation board
looks like the most straightforward option.
Looking at the datasheet, it looks like you are pushing it a bit hard
from the reference clock side of things. Using double-edge trigger is a
good way to upset things, as rising and falling edge, as detected, may
cause re-occuring stress in either direction, so it's not ideal.
Sniffing the loop at pin 31 would give you a hint if it is pumping every
50 ns or so.
I would consider of using a 100 MHz OCXO as an intermediate step. Lock
it to your 10 MHz in a high-bandwidth PI loop and then feed it to the
AD9912 board.
What is your tool of choice for checking the phase-noise?
Cheers,
Magnus
On 12/30/2013 9:37 AM, Gerhard Hoffmann wrote:
Driving the DDS system clock from an expensive RF generator (e.g. HP
8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply/cheaply.
Although expensive from a hobbyist viewpoint, the HP8648A is
far from HP/Agilent's best, and even the best (8662A) is still
not adequate to use as a clock in most cases. No general
purpose sig gen is. (disclaimer: I work for Agilent).
Rick Karlquist N6RK
Actually the Rohde SMA100A with opt B22 is pretty darn good, and Rick is being a bit humble, the Agilent E8663D is also very good.
I hope all member have a happy and prosperous new year.
Thomas Knox
Date: Tue, 31 Dec 2013 20:01:38 -0800
From: richard@karlquist.com
To: ghf@hoffmann-hochfrequenz.de; time-nuts@febo.com
Subject: Re: [time-nuts] sysclock source for AD9912 DDS?
On 12/30/2013 9:37 AM, Gerhard Hoffmann wrote:
Driving the DDS system clock from an expensive RF generator (e.g. HP
8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply/cheaply.
Although expensive from a hobbyist viewpoint, the HP8648A is
far from HP/Agilent's best, and even the best (8662A) is still
not adequate to use as a clock in most cases. No general
purpose sig gen is. (disclaimer: I work for Agilent).
Rick Karlquist N6RK
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