What is the best way to multiply a 10 Mhz
It would seem the most jitter free way to do it would be to simply
multiply it up like we used to do. Some reasonably Hi-Q LC circuits
could make a nice flywheel and filter out other signals at the same
time. Once you have it to the desired signal frequency you could
condition it to clock your DDS.
Am I missing something here? Wouldn't be the first time, ya know!
Burt, K6OQK
Subject: Re: [time-nuts] what is the best way to multiply a 10 Mhz
signal?
On 21/12/10 16:35, Stephen Farthing wrote:
Hi everyone,
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS at
70 Mhz. Has anyone tried this?
Regards,
Steve G0XAR
From: Eamon Skelton nospam@oceanfree.net
What is the application? What will the DDS output frequency be?
Maybe you could use a 70MHz (or whatever frequency you need)
VCO as the DDS clock and use the DDS as a programmable divider
to produce a 10MHz output. This could be phase locked to the
10MHz output from the LPRO-101.
Burt I. Weiner Associates
Broadcast Technical Services
Glendale, California U.S.A.
biwa@att.net
www.biwa.cc
K6OQK
So, two doublers for 40 MHz and a tripler for 30 and then
mix to get 70? What happens to phase noise when you do that?
Is it as bad as a PLL?
Seems like you ought to get adequate harmonic rejection.
What about six mixers to get 20, 30, 40, 50, 60, and 70 MHz?
Chips and tank coils are cheap, no?
Bill Hawkins
-----Original Message-----
From: Burt I. Weiner
Sent: Tuesday, December 21, 2010 1:39 PM
It would seem the most jitter free way to do it would be to simply
multiply it up like we used to do. Some reasonably Hi-Q LC circuits
could make a nice flywheel and filter out other signals at the same
time. Once you have it to the desired signal frequency you could
condition it to clock your DDS.
Am I missing something here? Wouldn't be the first time, ya know!
Burt, K6OQK
Subject: Re: [time-nuts] what is the best way to multiply a 10 Mhz
signal?
On 21/12/10 16:35, Stephen Farthing wrote:
Hi everyone,
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS
at
70 Mhz. Has anyone tried this?
Regards,
Steve G0XAR
Burt I. Weiner wrote:
It would seem the most jitter free way to do it would be to simply
multiply it up like we used to do. Some reasonably Hi-Q LC circuits
could make a nice flywheel and filter out other signals at the same
time. Once you have it to the desired signal frequency you could
condition it to clock your DDS.
Some experience here. At Zeta Labs, we made a lot of money
building such multipliers. It is surprisingly hard to do it
correctly and get low phase noise. At HP, the X6 multiplier
to 60 MHz in the 5065 and the X9 multipler in the 5060/1 were
full employment plans for production engineers, especially if
they were operating under the Peter Principle. HP definitely
knew less than Zeta about these things. The two examples of
doing it right at HP were the 8662A and 5071A which had doubler
chains. I never heard a peep from the production engineers
about the 5071A doubler chain that I designed. It just worked. Period.
The doubling was accomplished by wiring the LO and RF ports
of an ASK-1 mixer in series and driving it with a very well filtered
low distortion sine wave (important) at about 10 mW. The
output filtering was just a ladder of parallel resonant tanks
in shunt and series resonant tanks in series. The Q of the tanks
was fairly low. I used a fair number of them to get enough
filtering. Not a few high Q tanks as you typically see. There
were no (zero) adjustments.
Rick Karlquist N6RK
The 6 mixer scheme was my first thought for lowest PN. That way you do not
get 20logN, but you just get the RMS sum of the noise power each time. That
would be 3 dB to get to 20 MHz, and, each time the sum becomes less than 3
dB, as the highest frequency dominates. It would only degrade approximately
a total of 10 dB vs. the 17 dB from a regular times 7. Regards - Mike
Mike B. Feher, EOZ Inc.
89 Arnold Blvd.
Howell, NJ, 07731
732-886-5960 office
908-902-3831 cell
-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Bill Hawkins
Sent: Tuesday, December 21, 2010 2:55 PM
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] What is the best way to multiply a 10 Mhz
So, two doublers for 40 MHz and a tripler for 30 and then
mix to get 70? What happens to phase noise when you do that?
Is it as bad as a PLL?
Seems like you ought to get adequate harmonic rejection.
What about six mixers to get 20, 30, 40, 50, 60, and 70 MHz?
Chips and tank coils are cheap, no?
Bill Hawkins
-----Original Message-----
From: Burt I. Weiner
Sent: Tuesday, December 21, 2010 1:39 PM
It would seem the most jitter free way to do it would be to simply
multiply it up like we used to do. Some reasonably Hi-Q LC circuits
could make a nice flywheel and filter out other signals at the same
time. Once you have it to the desired signal frequency you could
condition it to clock your DDS.
Am I missing something here? Wouldn't be the first time, ya know!
Burt, K6OQK
Subject: Re: [time-nuts] what is the best way to multiply a 10 Mhz
signal?
On 21/12/10 16:35, Stephen Farthing wrote:
Hi everyone,
I want to multiply the output from my Efratom 101 (10Mhz) to clock a DDS
at
70 Mhz. Has anyone tried this?
Regards,
Steve G0XAR
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Mike Feher wrote:
The 6 mixer scheme was my first thought for lowest PN. That way you do not
get 20logN, but you just get the RMS sum of the noise power each time.
That
No, this is a fallacy because phase noise adds coherently, so that each
doubler adds 6 dB and each tripler adds 9.54 dB. There is no way to get
around 20 LOG N, no matter how you implement the multiplier even if
you add a tripler output to a quadrupler output, where phase noise also
adds coherently.
Rick Karlquist N6RK
Am 21.12.2010 21:41, schrieb Rick Karlquist:
No, this is a fallacy because phase noise adds coherently, so that each
doubler adds 6 dB and each tripler adds 9.54 dB. There is no way to get
around 20 LOG N, no matter how you implement the multiplier even if
you add a tripler output to a quadrupler output, where phase noise also
adds coherently.
Yes, it adds coherently because it stems from the same source.
It is easier to see in the time domain: 1ps of jitter on a 10 MHz carrier,
when multiplied to 100 MHz is still 1 ps of jitter, just look at the
zero crossings. But at 100 MHz, the jitter percentage of 1 ps to the 360°
is 10 times as bad, because the 360 degrees/s have shrunk.
So, a phase detector will give 10 times the output voltage or
20 dB more power. No way around this.
Gerhard, dk4xp
It is easier to see in the time domain: 1ps of jitter on a 10 MHz carrier,
when multiplied to 100 MHz is still 1 ps of jitter, just look at the
zero crossings. But at 100 MHz, the jitter percentage of 1 ps to the 360°
is 10 times as bad, because the 360 degrees/s have shrunk.
So, a phase detector will give 10 times the output voltage or
20 dB more power. No way around this.
I'm interested too because I have several of the same DDS chip that
I will want to drive from a 10Mhz GPSDO.
First off let's look at what the DDS chips needs. It wants a square
wave input an exact 50% duty cycle is not required. We do want very
low jitter in the clock.
OK I see how the above applies if you just look at one cycle of the
10MHz but my simple plan was to use a PLL with divide by 10 in the
filter but I figure you do better than you describe because there is a
low pass filter on the voltage that controls the 100Mhz VCO. So in
effect the controlling voltage is the running average of many phase
detection errors.
My plan was this...
- A 100 Mhz voltage controlled crystal oscillator will drive the DDS chip
- this same 100MHz is also divided by 10 and sent to phase detector in PLL chip
- error signal from chip goes to low pass filter them to the 100Mhz VCXO.
I think this is 100% "classic" PLL multiplier design that goes back
decades. As I understand it this can work well if my VCXO is stable
over a period of 30 minutes or so. I think al the"smarts" is in
picking the time constant for the low pass filter.
--
Chris Albertson
Redondo Beach, California
Clarification of my previous posting:
The IF output of the ASK-1 should be pins 2 and 5,
not pins 4 and 5.
The LO input of the ASK-1 is pins 1 and 3.
The RF input of the ASK-1 is pins 4 and 6.
This is not obvious from the data sheet.
You can wire these two ports in series any
way you like, actually. Series works
better than shunt or using a power divider,
or quadrature hybrid, according to my lab
tests ~15 years ago.
Rick Karlquist N6RK