Hi, Over time, my UBX-160 modules run hot, up to concerning levels (ribbed heat plate of one or both sometimes run too hot to touch). The temperature of the FPGA heatsink does not seem to be a problem. The metal lid of the X310 is on to push the air over both modules, vents on both sides are ofcourse free. I would like to reduce the heat and perhaps powerconsumption of the X310 and the daugtherboards to moderate levels, also to get the best analog phase and SNR performance, while downconverting a wideband signal around 1420.405751786 MHz (hydrogen line). For this purpose, I will not need to use the transmitter part. On the software and FPGA side, I'd figure some bias currents might be switched off or reduced, perhaps clocks and modulatators/demodulators to the unused parts of the UBX-160 could be turned off if not already turned off. 1) There are two additional 12V headers on the X310 mainboard, W3 and W4, are there additional fans available for these, how much can be drawn ? I have used both an RFNoC based bitstream and the mainbranch. I performed calibration of DC offsets, rx and tx iq balance, for both modules and the ADCs they are instaled on, independently. I terminated all RF inputs with 50 ohm. I have no GPSDO installed, instead I'm using an external 10 MHz rubidium reference or the (hardwired?) internal oscillator. 2) I'm missing configuration options when using RFNoC regarding external clocksources for both radio inputs. Is there more documentation or some other hints in sourcecode for this ? Best, Mark-Jan

Hi Mark-Jan, I can't speak to the RFNoC question, but there are ways to reduce power on the UBX board. First, the UBX has a "power_mode" setting that can disable certain frontend components when not streaming. To do this, add the following lines of code: BOOST_FOREACH(size_t mboard, usrp->get_num_mboards) { usrp->get_device()->get_tree().access<std::string>("/mboards" / mboard / "dboards/A/rx_frontends/0/power_mode").set("powersave"); usrp->get_device()->get_tree().access<std::string>("/mboards" / mboard / "dboards/B/rx_frontends/0/power_mode").set("powersave"); } In "powersave" mode, the UBX will only enable the frontend components when streaming so settling time will be longer. The default is "performance" mode, which keeps the frontend components enabled. Beyond that, you can modify the UHD code to shutdown the TX side LOs. Just add the following code at the end of the UBX initialization (at line https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/dboard/db_ubx.cpp#L465 ): _txlo1->shutdown(); _txlo2->shutdown(); Regards, Michael On Sat, Jan 30, 2016 at 6:24 AM, Mark-Jan Bastian via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > Over time, my UBX-160 modules run hot, up to concerning levels (ribbed > heat plate of one or both sometimes run too hot to touch). > The temperature of the FPGA heatsink does not seem to be a problem. The > metal lid of the X310 is on to push the air over both modules, vents on > both sides are ofcourse free. > > I would like to reduce the heat and perhaps powerconsumption of the X310 > and the daugtherboards to moderate levels, also to get the best analog > phase and SNR performance, while downconverting a wideband signal around > 1420.405751786 MHz (hydrogen line). For this purpose, I will not need > to use the transmitter part. > > On the software and FPGA side, I'd figure some bias currents might be > switched off or reduced, perhaps clocks and modulatators/demodulators > to the unused parts of the UBX-160 could be turned off if not already > turned off. > > 1) There are two additional 12V headers on the X310 mainboard, W3 and W4, > are there additional fans available for these, how much can be drawn ? > > I have used both an RFNoC based bitstream and the mainbranch. > I performed calibration of DC offsets, rx and tx iq balance, > for both modules and the ADCs they are instaled on, independently. > I terminated all RF inputs with 50 ohm. > I have no GPSDO installed, instead I'm using an external 10 MHz rubidium > reference or the (hardwired?) internal oscillator. > > 2) I'm missing configuration options when using RFNoC regarding > external clocksources for both radio inputs. Is there more documentation > or some other hints in sourcecode for this ? > > Best, > > Mark-Jan > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

Hi Michael, I'm building a TDMA system with UHD and found strong leakages from Tx slot to Rx slot of UBX than of SBX. I try to turn on the powersave mode of UBX with: usrp->get_device()->get_tree()->access<std::string>("/mboards/0/dboards/A/rx_frontends/0/power_mode/").set("powersave"); but I get runtime error: Error: RuntimeError: Cannot access! Property uninitialized at: /mboards/0/dboards/A/rx_frontends/0/power_mode/ Would you tell the correct setting for turning on the powersave mode? Thank you. I'm using x310+UBX-160 with fresh 3.9.4-release UHD and image. Br, Hanwen 2016-02-01 20:38 GMT+01:00 Michael West via USRP-users < usrp-users@lists.ettus.com>: > Hi Mark-Jan, > > I can't speak to the RFNoC question, but there are ways to reduce power on > the UBX board. First, the UBX has a "power_mode" setting that can disable > certain frontend components when not streaming. To do this, add the > following lines of code: > > BOOST_FOREACH(size_t mboard, usrp->get_num_mboards) > { > usrp->get_device()->get_tree().access<std::string>("/mboards" / mboard > / "dboards/A/rx_frontends/0/power_mode").set("powersave"); > usrp->get_device()->get_tree().access<std::string>("/mboards" / mboard > / "dboards/B/rx_frontends/0/power_mode").set("powersave"); > } > > In "powersave" mode, the UBX will only enable the frontend components when > streaming so settling time will be longer. The default is "performance" > mode, which keeps the frontend components enabled. > > Beyond that, you can modify the UHD code to shutdown the TX side LOs. > Just add the following code at the end of the UBX initialization (at line > https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/dboard/db_ubx.cpp#L465 > ): > > _txlo1->shutdown(); > _txlo2->shutdown(); > > Regards, > Michael > > On Sat, Jan 30, 2016 at 6:24 AM, Mark-Jan Bastian via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> >> Over time, my UBX-160 modules run hot, up to concerning levels (ribbed >> heat plate of one or both sometimes run too hot to touch). >> The temperature of the FPGA heatsink does not seem to be a problem. The >> metal lid of the X310 is on to push the air over both modules, vents on >> both sides are ofcourse free. >> >> I would like to reduce the heat and perhaps powerconsumption of the X310 >> and the daugtherboards to moderate levels, also to get the best analog >> phase and SNR performance, while downconverting a wideband signal around >> 1420.405751786 MHz (hydrogen line). For this purpose, I will not need >> to use the transmitter part. >> >> On the software and FPGA side, I'd figure some bias currents might be >> switched off or reduced, perhaps clocks and modulatators/demodulators >> to the unused parts of the UBX-160 could be turned off if not already >> turned off. >> >> 1) There are two additional 12V headers on the X310 mainboard, W3 and W4, >> are there additional fans available for these, how much can be drawn ? >> >> I have used both an RFNoC based bitstream and the mainbranch. >> I performed calibration of DC offsets, rx and tx iq balance, >> for both modules and the ADCs they are instaled on, independently. >> I terminated all RF inputs with 50 ohm. >> I have no GPSDO installed, instead I'm using an external 10 MHz rubidium >> reference or the (hardwired?) internal oscillator. >> >> 2) I'm missing configuration options when using RFNoC regarding >> external clocksources for both radio inputs. Is there more documentation >> or some other hints in sourcecode for this ? >> >> Best, >> >> Mark-Jan >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Hi Hanwen, Sorry, I forgot the "/value" at the end of the path. It should be: usrp->get_device()->get_tree()->access<std::string>("/mboards/0/dboards/A/rx_frontends/0/power_mode/value").set("powersave"); You can see the paths to all the properties in the tree by running "uhd_usrp_probe --tree". Regards, Michael On Sun, May 8, 2016 at 2:39 AM, hanwen <kidult.hanwen@gmail.com> wrote: > Hi Michael, > > I'm building a TDMA system with UHD and found strong leakages from Tx slot > to Rx slot of UBX than of SBX. I try to turn on the powersave mode of UBX > with: > > usrp->get_device()->get_tree()->access<std::string>("/mboards/0/dboards/A/rx_frontends/0/power_mode/").set("powersave"); > but I get runtime error: Error: RuntimeError: Cannot access! Property > uninitialized at: /mboards/0/dboards/A/rx_frontends/0/power_mode/ > > Would you tell the correct setting for turning on the powersave mode? > Thank you. > > I'm using x310+UBX-160 with fresh 3.9.4-release UHD and image. > > Br, Hanwen > > > > 2016-02-01 20:38 GMT+01:00 Michael West via USRP-users < > usrp-users@lists.ettus.com>: > >> Hi Mark-Jan, >> >> I can't speak to the RFNoC question, but there are ways to reduce power >> on the UBX board. First, the UBX has a "power_mode" setting that can >> disable certain frontend components when not streaming. To do this, add >> the following lines of code: >> >> BOOST_FOREACH(size_t mboard, usrp->get_num_mboards) >> { >> usrp->get_device()->get_tree().access<std::string>("/mboards" / >> mboard / "dboards/A/rx_frontends/0/power_mode").set("powersave"); >> usrp->get_device()->get_tree().access<std::string>("/mboards" / >> mboard / "dboards/B/rx_frontends/0/power_mode").set("powersave"); >> } >> >> In "powersave" mode, the UBX will only enable the frontend components >> when streaming so settling time will be longer. The default is >> "performance" mode, which keeps the frontend components enabled. >> >> Beyond that, you can modify the UHD code to shutdown the TX side LOs. >> Just add the following code at the end of the UBX initialization (at line >> https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/dboard/db_ubx.cpp#L465 >> ): >> >> _txlo1->shutdown(); >> _txlo2->shutdown(); >> >> Regards, >> Michael >> >> On Sat, Jan 30, 2016 at 6:24 AM, Mark-Jan Bastian via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Hi, >>> >>> Over time, my UBX-160 modules run hot, up to concerning levels (ribbed >>> heat plate of one or both sometimes run too hot to touch). >>> The temperature of the FPGA heatsink does not seem to be a problem. The >>> metal lid of the X310 is on to push the air over both modules, vents on >>> both sides are ofcourse free. >>> >>> I would like to reduce the heat and perhaps powerconsumption of the X310 >>> and the daugtherboards to moderate levels, also to get the best analog >>> phase and SNR performance, while downconverting a wideband signal around >>> 1420.405751786 MHz (hydrogen line). For this purpose, I will not need >>> to use the transmitter part. >>> >>> On the software and FPGA side, I'd figure some bias currents might be >>> switched off or reduced, perhaps clocks and modulatators/demodulators >>> to the unused parts of the UBX-160 could be turned off if not already >>> turned off. >>> >>> 1) There are two additional 12V headers on the X310 mainboard, W3 and W4, >>> are there additional fans available for these, how much can be drawn ? >>> >>> I have used both an RFNoC based bitstream and the mainbranch. >>> I performed calibration of DC offsets, rx and tx iq balance, >>> for both modules and the ADCs they are instaled on, independently. >>> I terminated all RF inputs with 50 ohm. >>> I have no GPSDO installed, instead I'm using an external 10 MHz rubidium >>> reference or the (hardwired?) internal oscillator. >>> >>> 2) I'm missing configuration options when using RFNoC regarding >>> external clocksources for both radio inputs. Is there more documentation >>> or some other hints in sourcecode for this ? >>> >>> Best, >>> >>> Mark-Jan >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >