is there a "best bet" advanced hobbyist buildable GPSDO design?
Scott Burris wrote:
Yes! I now feel inspired to go spin a design after studying all of
these messages in this
thread. My only constraint is that the parts have to pass the "Digikey"
test, i.e. I have to
be able to order small quantities from Digikey, Mouser, or the like.
It's nearly impossible
for a hobbyist like me to get small quantities of more exotic parts.
The big distributors have
gotten better in the last decade about taking small orders, but still
often have minimum qty/piece
requirements that they won't waive. Even worse are orderable, but
unobtainable parts -- Maxim
seems to have a huge library of such "virtual" chips that have lead
times of 1/2 year or more.
Scott
Scott
On checking the Mouser and Digikey websites the DS1020 series
programmable delay lines are non stock items.
However I can obtain the DS1020-25 locally from RS Components.
The D1020-15 would be preferable for use with an M12M GPS timing
receiver, however the DS1020-25 could be used.
Maybe we need to consider using a CPLD or another implementation (eg
ramp generator plus DAC (8bit) and comparator).
Analog Devices used to make a single chip implementation of the ramp
plus DAC and comparator programmable delay system.
However such devices need to be calibrated, preferably continuously.
The saving grace is that with a dedicated processor, there's plenty of
time and processing power to do this once a second (between successive
PPS pulses).
Calibration technique is simple:
-
Adjust the programmed delay so that the programmed delay is exactly 1
(OCXO) clock period record the DAC data required to achieve this. -
Adjust the programmed delay so that the programmed delay is exactly 2
(OCXO) clock periods, record the DAC data required to achieve this. -
calculate the OFFSET and GAIN parameters from the above data.
Of course such a scheme can be elaborated to include delays greater than
a couple clock periods and exponential averaging of results can be
employed to reduce the noise.
The calibration technique assumes that the delay is a linear function of
the DAC input.
A D flipflop plus some additional logic (synchroniser) can be used to
detect coincidence between the clock edge and the output of the delay
device.
Bruce
Bruce Griffiths wrote:
As far as I know Dallas/Maxim appears to be the only source of suitable
affordable programmable delay chips for this particular application.
In principle one could use a tapped chain of gates in a CPLD, however
continuous calibration of the delay is required (a delay locked loop
controlling the gate propagation delay by adjusting its power supply
voltage to compensate for the effect of temperature variations is one
technique). However unless the Dallas chips become hard to obtain its
probably best to leave this as a backup option.
What about sending the 1PPS signal through a number of HC family gates
and using a mux
to select a tap -- is that better than using a CPLD? Hmm, probably the
delay varies too much from manufacturer to manufacturer
to make this work reliably. Probably temperature sensitive too.
What kind of delay characteristics are needed? I see some other delay
lines with 100ps
steps available, see:
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=408-1127-ND
and put that through a mux?
Looks like some of the DS1020's are available through Maxim's e-commerce
site, but some have
a 15 week lead time, depending on the particular model.
What processor are you intending to use to decipher the sawtooth
correction messages from the GPS timing receiver?
You could use an inexpensive microprocessor dedicated to this simple task.
Another microprocessor can be used to discipline the OCXO.
Depending on your experience, this can be easier than using a single
microprocessor to do everything.
I have experience with PICs, Atmel AVRs, and various ARM flavors, and
limited experience
with SOC processors in Xilinx FPGAs (Picoblaze and the like). PICs and
AVRs are cheap, so no problem
dedicating one to this task.
Anyone have a list of GPS units which provide sawtooth correction data?
I have a few flavors of
Motorola products and a Trimble Lassen IQ laying around. They all
provide 1PPS signals, but I bet
some don't have the necessary features.
Scott
Hi Michael,
Yes that may be true (but I did not test any of that...)
Well... with digital prog. logic devices that operate
at similar speed than HC and AC should be true yes.
On the fast CPLDs that run past 300MHz the jitter
should have scale down proportionally (I imagine)
but I have no clue if that is similar, better or still
worst than HC or AC.
Yeap... Nice thing to test
Hummm... I'm still thinking how to test such... :-)
Luis Cupido.
ct1dmk.
michael taylor wrote:
On Dec 12, 2007 7:33 AM, Luis Cupido cupido@mail.ua.pt wrote:
Very good, I do respect the usage of a bunch of CMOS/TTL chips if
someone doesn't want to spend the
effort of learning how to use a CPLD. When it comes to use CPUs for
tasks better done by straight logic (and there are many examples
out there) then I think it is not the right option.
All understood so let's not discuss that any further.
Bruce also alludes to the higher jitters of CPLD versus Advanced/High
Speed CMOS logic gates (AC or HC families).
This has to do with the programmable nature of CPLD / FPGA ICs as I
understand it.
Ref: http://www.febo.com/pipermail/time-nuts/2007-April/025299.html
-Michael
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Ok. I understand now what you suggest.
Thanks for the explanation.
Luis Cupido.
ct1dmk.
Bruce Griffiths wrote:
Luis Cupido wrote:
Bruce,
No analog filtering of the D flipflop output is required.
Now you got me lost.
We were talking about a GPSDO, that is locking
an VCXO on the GPS time (1pps or else)
So by the end of it you need an analog
signal to control the voltage input of the VCXO. Right ?
Where you get that from ?
If not by filtering your flip-flop output
what else you have in between the 1pps and the VCXO ?
CPU's DAC's ????
Some software, including a sigma delta DAC, the effect of which is no
different, in principle, than the filtering etc required by any of your
phase detector implementations.
The 1 bit phase error samples are processed in software (or hardware
depending on one's inclinations, expertise, etc) in a similar way that
samples from an N (>1) phase detector samples are, to produce a digital
output for a DAC which drives the OCXO EFC input. The only difference is
that a sigma delta DAC is used instead of a conventional DAC.
if so how does your complexity arguments still apply ?
The interpretation of "complexity " depends on ones background and
experience.
The originator of the thread indicated that they had some microprocessor
software experience.
Luis Cupido
I was trying to tailor the design to the stated strengths of the
originator of the thread.
If one is trying to "squeeze" the ultimate in performance when using a
GPS receiver to discipline an OCXO, then carrier phase measurements
potentially offer much higher performance than can be achieved by using
the PPS output of a typical GPS timing receiver.
However only a few commercially available GPS receivers are suitable for
this application.
The GPS receiver oscillators all have to be phase locked to the OCXO
being disciplined.
This approach has been used in at least one commercially available GPSDOCXO.
In principle a GPS receiver has all the required measurement hardware,
so all that is required are suitable algorithms implemented in either
software running on a DSP, microprocessor, etc, or implemented in
hardware (CPLD etc).
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Scott
Scott Burris wrote:
Bruce Griffiths wrote:
As far as I know Dallas/Maxim appears to be the only source of suitable
affordable programmable delay chips for this particular application.
In principle one could use a tapped chain of gates in a CPLD, however
continuous calibration of the delay is required (a delay locked loop
controlling the gate propagation delay by adjusting its power supply
voltage to compensate for the effect of temperature variations is one
technique). However unless the Dallas chips become hard to obtain its
probably best to leave this as a backup option.
What about sending the 1PPS signal through a number of HC family gates
and using a mux
to select a tap -- is that better than using a CPLD? Hmm, probably the
delay varies too much from manufacturer to manufacturer
to make this work reliably. Probably temperature sensitive too.
All of the above, however the major problems are that the individual
gate delay is too long and the designing a suitable multiplexer isnt easy.
I dont think that cascading 30 or more 1ns delay gates all in different
packages is going to work that well.
CPLDs have the advantage that to a first approximation all the gate
delays are identical.
However you have to force the configuration to interconnect them
appropriately software so as not to spoil the performance.
What kind of delay characteristics are needed? I see some other delay
lines with 100ps
steps available, see:
With an M12+T you need a minimum variable delay range of about 20ns or
so with a step size, accuracy and stability of better than 1ns
(resolution of sawtooth correction message) to avoid degrading performance.
Tom Clark suggested that the DS1020-15 with 150ps resolution is OK for
this receiver, however it needs to be calibrated over the delay range used.
Other receivers (particularly older ones) will need larger delay ranges.
The required delay range is around 0.5 to 1x the receiver timing clock
period for the Motorola receivers.
Autocalibration techniques can be used to track the effects of
temperature and aging.
http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=408-1127-ND
and put that through a mux?
In principle this would work, the devil lies in the detail of the mux
design.
The mux delay needs to be independent of the selected tap.
The delay range provided by one of these devices is too small.
As a fallback option I have produced a draft schematic of a ramp style
delay generator with a resolution of 100ps and a range of 400ns or so.
The extended range allows calibration against a 10MHz OCXO derived clock
and should allow it to be used with most of the older Motorola Timing
receivers that provide sawtooth correction data.
Such calibrations can be interleaved between successive PPS pulses.
A 12 bit resolution DAC with a settling time (to 0.01%) of around
100millisec or so is required for this DAC.
It may be feasible to use a PWM DAC for this.
Looks like some of the DS1020's are available through Maxim's e-commerce
site, but some have
a 15 week lead time, depending on the particular model.
What processor are you intending to use to decipher the sawtooth
correction messages from the GPS timing receiver?
You could use an inexpensive microprocessor dedicated to this simple task.
Another microprocessor can be used to discipline the OCXO.
Depending on your experience, this can be easier than using a single
microprocessor to do everything.
I have experience with PICs, Atmel AVRs, and various ARM flavors, and
limited experience
with SOC processors in Xilinx FPGAs (Picoblaze and the like). PICs and
AVRs are cheap, so no problem
dedicating one to this task.
Anyone have a list of GPS units which provide sawtooth correction data?
I have a few flavors of
Motorola products and a Trimble Lassen IQ laying around. They all
provide 1PPS signals, but I bet
some don't have the necessary features.
M12MT, M12+T, Trimble Resolution-T all provide sawtooth correction data.
Scott
Bruce
Scott
Data delay devices (http://www.datadelay.com) also do programmable delay
lines their minimum order is $US75 which isnt too bad particularly if
more than one sawtooth corrector is to be built.
They even do ECL programmable delays as do Micrel (http://www.micrel.com).
However these ECL programmable delay devices dont have enough range for
this application.
If you solve the multiplexer problem and use embedded calibration you
could use circuit board traces to implement the delay line sections,
however a lot of PCB real estate would be required.
Such delays also have significant tempcos when using fibre glass PCB
substrates.
Bruce
On Dec 12, 2007 2:32 AM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Michael
The analog circuitry for a sigma-delta DAC is attached.
The input is optically isolated using a high speed low jitter CMOS
optocoupler (Avago produce an equivalent device) to break low frequency
ground loops.
I was wondering if the Avago HCPL-9000 or Analog's ADUM1100 iCoupler
would be suitable alternatives to the HCPL-7100.
Similarly an RF transformer should be used to couple the OCXO output to
the Digital board breaking another potential low frequency ground loop.
For the RF transformer I am considering a Coilcraft WB1-6(S)L
transformer to decouple the OCXO output.
http://www.coilcraft.com/wb_th.cfm
I want to do some more reading, but I think I'm might have some
questions about DAC input data (from the microprocessor).
Would there be any problems, or benefits to using AHC versus AC logic
family flipflops and the inverting Schmitt triggers?
In regards to the sawtooth correction, I am undecided. If I understand
correctly, even without not addressing it there should be an
improvement over existing public designs (Shera, Miller). If I
remember correctly, you were keen on a software/firmware based
sawtooth approach, if so that might be more flexible and cheaper than
fiddling with a uncalibrated DS1020 delay line.
Thank you,
Michael
Michael
michael taylor wrote:
On Dec 12, 2007 2:32 AM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Michael
The analog circuitry for a sigma-delta DAC is attached.
The input is optically isolated using a high speed low jitter CMOS
optocoupler (Avago produce an equivalent device) to break low frequency
ground loops.
I was wondering if the Avago HCPL-9000 or Analog's ADUM1100 iCoupler
would be suitable alternatives to the HCPL-7100.
Check the jitter, no jitter specs given for the iCouplers.
You may have to measure it on a sample.
The HCPL9000 should be fine but measure the jitter.
Circuit is actually reasonably tolerant to jitter as the low pass filter
averages such effects over many cycles.
If jitter proves a problem then if the micro or other logic generating
the sigma delta DAC bit-stream is clocked by the OCXO a D flipflop can
be used to retime the bitstream after the optocoupler/isolator reducing
the bit stream jitter to a few tens of picoseconds or so.
Similarly an RF transformer should be used to couple the OCXO output to
the Digital board breaking another potential low frequency ground loop.
For the RF transformer I am considering a Coilcraft WB1-6(S)L
transformer to decouple the OCXO output.
http://www.coilcraft.com/wb_th.cfm
Probably OK although there appear to be no VSWR specs for these.
I want to do some more reading, but I think I'm might have some
questions about DAC input data (from the microprocessor).
Would there be any problems, or benefits to using AHC versus AC logic
family flipflops and the inverting Schmitt triggers?
Whilst HC logic performance is adequate there is probably not too much
harm in using AHC or even AC as long as you use a ground plane together
with suitable layout techniques.
Metastability rates would go down by a large factor however the rate
with HC logic should be well below once every 1E10 years.
In regards to the sawtooth correction, I am undecided. If I understand
correctly, even without not addressing it there should be an
improvement over existing public designs (Shera, Miller). If I
remember correctly, you were keen on a software/firmware based
sawtooth approach, if so that might be more flexible and cheaper than
fiddling with a uncalibrated DS1020 delay line.
Depends on the entire system cost a single chip programmable delay plus
a D flipflop and little else should be cheaper than most high resolution
phase detector approaches.
As long as one can calibrate the DS1020 to improve its performance over
the datasheet specs. If it is sufficient to do this once (using a 5370
or equivalent) then the cost may be lower.
There are a lot of legacy devices/systems in use that actually require a
low jitter PPS pulse.
Most phase detectors with resolution, stability and accuracy better than
1ns (needs to be better than 500ps or so avoid significantly degrading
the quality of the correction) also require calibration unless one has a
suitable (2??) GHz clock (or equivalent) locked to the OCXO being
disciplined.
1ns accuracy and stability are perhaps easier to achieve when using a
sampled quadrature pair sine wave interpolator but even this requires
significant support logic to facilitate measuring harmonic content ,
quadrature error etc.
Thank you,
Michael
Bruce
Bruce Griffiths wrote:
On checking the Mouser and Digikey websites the DS1020 series
programmable delay lines are non stock items.
However I can obtain the DS1020-25 locally from RS Components.
The D1020-15 would be preferable for use with an M12M GPS timing
receiver, however the DS1020-25 could be used.
Maybe we need to consider using a CPLD or another implementation (eg
ramp generator plus DAC (8bit) and comparator).
Analog Devices used to make a single chip implementation of the ramp
plus DAC and comparator programmable delay system.
However such devices need to be calibrated, preferably continuously.
The saving grace is that with a dedicated processor, there's plenty of
time and processing power to do this once a second (between successive
PPS pulses).
Calibration technique is simple:
-
Adjust the programmed delay so that the programmed delay is exactly 1
(OCXO) clock period record the DAC data required to achieve this. -
Adjust the programmed delay so that the programmed delay is exactly 2
(OCXO) clock periods, record the DAC data required to achieve this. -
calculate the OFFSET and GAIN parameters from the above data.
Of course such a scheme can be elaborated to include delays greater than
a couple clock periods and exponential averaging of results can be
employed to reduce the noise.
The calibration technique assumes that the delay is a linear function of
the DAC input.
A D flipflop plus some additional logic (synchroniser) can be used to
detect coincidence between the clock edge and the output of the delay
device.
Continuing the design discussions, anyone have opinions about powering
the HP 10811 oscillator?
I'm thinking that you want voltage regulators that are pretty quiet so
as to minimize jitter introduced
via the power supply. To that end, I'm looking at a LT1761 for the +12v
OSC voltage and an LT3080
for the 24v heater supply.
In reading the 10811 manual, the heater and oscillator are isolated, yet
the example power supply ties
both together in a common ground. That certainly would make things
simpler, as a 24VCT transformer
could be used, and +12 and +24 volts could be made pretty naturally that
way.
How important in a GPSDO application is it to keep these two sections
completely isolated? I figure I would
either have to use a small HF transformer with a chopper circuit or a
separate 60hz transformer for the second
voltage.
Scott
On Dec 13, 2007 12:00 PM, Scott Burris slburris@gmail.com wrote:
Continuing the design discussions, anyone have opinions about powering
the HP 10811 oscillator?
I'm thinking that you want voltage regulators that are pretty quiet so
as to minimize jitter introduced
via the power supply. To that end, I'm looking at a LT1761 for the +12v
OSC voltage and an LT3080
for the 24v heater supply.
You may want to read some related discussion from the archives, about
powering a Rb oscillator (different specs, similar concerns).
http://www.febo.com/pipermail/time-nuts/2007-October/027906.html
I didn't notice what the tempco is like for those LDO regulators, I
don't know if it is worth considering a (buried Zener) voltage
reference.
-Michael