Scott,

Hard to say which is better at this point; there are a number
of variables, not the least of which is the intrinsic short-term
stability of the OCXO you use.

Do have a close look at James Miller's GPSDO:

http://www.jrmiller.demon.co.uk/projects/freqstd/frqstd.htm

I recently tested one and it makes it to 1e-13 at one day, which
is really nice for a simple, cheap, homebrew GPSDO.

/tvb

Scott, you have also:
http://w3ref.cfn.ist.utl.pt/cupido/reflock.html

lab grade consider using reflock II
for kits I think TAPR still has those...

Luis Cupido
ct1dmk.

Scott Burris wrote:

Tom Van Baak wrote:

Tom

What about the short term performance?
Its relatively easy to achieve a stability of 1E-13 for an averaging
time of 1 day, achieving good short or medium term stability is more
difficult.

If you want simplicity and higher performance you can do far better with
fewer parts,
An expensive high resolution DAC can be replaced with a software
sigma-delta DAC that has higher resolution.
The complex phase detector can be replaced with a D flipflop.
Add a microprocessor plus an opamp or 2 to filter and scale the EFC
voltage and thats about all thats required in addition to a good GPS
timing receiver.
For improved performance a hardware circuit to correct the PPS sawtooth
error will improve the medium term stability significantly when using a
high performance GPS timing receiver that provides an estimate of this
error.

Both the Brooks Shera and the James Miller designs have inadequate phase
error measurement resolution to achieve good short and medium term
stability.
However, this is only noticeable when using high performance GPS timing
receivers (M12+T, M12MT etc) and a high quality OCXO (10811A etc).

Bruce

On Dec 11, 2007 12:53 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz
wrote:

OK, so for the DAC piece, why not just use an NXP LPC ARM chip for the
microcontroller, and use a 32bit PCM output followed by a low pass filter as
the VXCO EFC?  The DAC just needs high resolution, not accuracy, right?
Or would the switching noise from the processor modulate the control
voltage?
I would hope the filter would clean any such noise, but I'll be the first to
admit
that the farther we get into the analog domain, the more I'm out of my
comfort zone.

I'm still trying to wrap my brain around the phase detection piece of this.
I've studied the Shera controller with it's 24Mhz oscillator and divided
down
sample of the VXCO and I'm can't get past thinking that this ends up
adding jitter.  With more modern parts can't the phase be measured more
directly?  What about sampling both the VXCO and 1PPS at a 200MHZ rate?
That should determine the phase difference within no more than a 10ns
inaccuracy.

Or use a pulse stretching technique to amplify the short time intervals into
something
more easily measured, although that's beyond what I'm familiar with.

I've read the PTTI presentation about using a DS1020 delay line to
de-sawtooth the
1PPS signal -- that's a pretty interesting idea.  At least the chip is
available in Qty 1,
at $30!

It just seems that the designs I've seen could use a refresh with some more
modern
circuitry.  At the very least the Shera controller could have much of its
logic put into
a single CPLD these days.

Scott

Scott

Scott Burris wrote:

True, but a Sigma delta DAC has far superior performance to a PWM DAC or
a standard DAC especially when the long term stability is not critical
and a faast response isnt required.
NIST use sigma delta DACs in their precision AC waveform generator and
to calibrate their Johnson noise thermometer systems.

Its best to have the processor drive an external current steering switch
(74HC4053) to switch a stable current into the summing junction of an
inverting opamp.
If you want I can send you a suitable circuit schematic.
With a suitable circuit one can just use a voltage reference and a
resistor to set the current, a spare  analog switch can be used in
series with the feedback resistor to provide temperature compensation
(important for good short and medium term stability). HP/Agilent in
effect use a similar temperature compensated current steering technique
in their 34401A 6.5 digit DVM.
Ulrich has uses similar techniques albeit with the sigma delta DAC logic
implemented in a gate array to achieve high resolution and good short
term stability.
In this application the DAC need not respond as fast so it can be
implemented in software.

Eliminate such unnecessary cost and complexity with a single D flipflop
phase detector (D connected to 10MHz signal or a divided down
subharmonic thereof, CLK connected to PPS) the circuit will
automatically adapt to achieve a resolution determined by the PPS jitter
(picoseconds if you have a good enough PPS source, a few nanosec with a
sawtooth corrected PPS signal from an M12M timing receiver, a few tens
of nanosec with an uncorrected PPS signal from an M12M timing receiver).
Thus its resolution is far better than when using a 24MHz clock and its
also cheaper and the hardware is less complex. Using a 200MHz clock just
increases the cost and power consumption without significant benefit
over the simpler D flipflop phase detector.
However you will need to write suitable software to process the D
flipflop output samples.

Again easily done but more complex than required.

That is a very good idea for getting the maximum performance with a D
flipflop phase detector and an M12M or similar GPS timing receiver.
You can do far better when using GPS carrier phase disciplining
techniques and the GPS receiver has all the necessary high resolution
phase measurement circuitry built in.
However considerable software development is required together with a
GPS receiver that makes the GPS carrier phase measurement data available.

The Shera controller is a dead end, it doesnt have sufficient resolution
and whilst increasing its resolution is possible there are simpler,
better and cheaper ways to achieve this.

Bruce

Hi Bruce and Scott.

Simplicity is good but when using a CPLD or an FPGA no need to get
simple if a better design still fits inside the chip ;-)

Indeed those style of phase measuring schemes have far better
performance than the simple flip flop or similar.

I say this because I had all the logic on a CPLD to play with
so I tried a large number of phase locking schemes and
could compare them.

First of all the lock capture range can become a bit
independent of the integration time with a proportional phase lag
counting method. Some counting methods will inherently search for lock
when lock is lost. Some of those methods also have lock acquisition
times orders of magnitude smaller.

On the other hand on CPLD (or FPGA) complexity doesn't cost more as
this stuff is ultra extra small considering the size of
a today's CPLD (eg. maxII w/ 1570 macrocells). No matter what you do
a medium CPLD will be only used 10 to 20% not more.

What I use on the reflock II is a time lag counter from the 1pps to
next clock, and this value drive a dac. Only a small integration time
is done digitally and the large integration time if one requires that
is done with a classical R and C without any active components right
before the Vtune of the VCXO. Therefore not a big DAC resolution is
required (I use 12-14bit) since the averaging is on the outside in an
analog filter in which simple 64 seconds integration time will grant
you 6 bit more resolution.

It may look a strange combination of a modern devices and a old
fashioned filter but it had by far outperformed all the designs I could
test w/ microporcessors + dac (in which some noise did get through),
or lack stability.

Luis Cupido
ct1dmk.
http://w3ref.cfn.ist.utl.pt/cupido/

Bruce Griffiths wrote:

On Dec 11, 2007 3:53 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

You have made similar comments about I believe the same approach in
the past. I was wondering if you have ever sketched out a schematic,
even if only rough. Perhaps with a few suggested components to try
(i.e. DAC, Op-Amp) that would be a good starting point for anyone who
wanted to prototype and evaluate the performance of this approach.

It is beyond my elementary design abilities to convert your
description into a well implemented design on my own, but I would be
interested in try to at least see if I could construct an unit using
these suggested techniques.

-Michael

michael taylor wrote:

Michael

Will provide a suitable circuit schematic for the DAC portion by around
1300 UTC.
The circuit will be suitable for either a PWM or a sigma-delta DAC.
The design will also include the ability to set (by selecting the values
of a couple of resistors) the EFC range to suit most OCXOs.

A sigma-delta DAC has the advantage that its easier to filter its output
than that of an equivalent resolution PWM DAC.

Combining a pair of lower resolution DACs with a few resistors will
produce a higher resolution output, however there will be problems with
monotonicity (when the coarse DAC output changes) unless the system is
periodically calibrated to  accommodate drifts due to temperature and
time. This can of course be done in software (no need for external
trimmers) however the calibration circuitry adds considerable complexity.

When testing the sigma delta DAC concept in software start with a simple
first order sigma delta modulator and then try a second order modulator
(dont go to higher order than a 2nd order modulator as they arent
necessary for this application and stabilisation of high order
modulators adds considerable complexity and can be difficult to achieve).

A suitable D flipflop phase detector design will follow shortly thereafter.

Do you also want a circuit for a sawtooth corrector using one of the
Maxim/Dallas programmable delay lines?

You will need to write the software for the sawtooth corrector and for
the D flip flop phase detector.
However I can provide descriptions of what the software needs to do,
along with suggestions for suitable algorithms.

Bruce

Luis

Luis Cupido wrote:

Not true, the effective measurement noise is only a few percent less
than that of a single bit phase detector (D flipflop) better with an
infinite resolution phase detector so why bother.
Single bit and 3 level ADCs are widely used in radio astronomy as except
when interference is a problem, multibit ADCs offer no significant
advantage.

By all means try them, but why add the power consumption and complexity
of a CPLD if it offers little improvement in performance?

If you are going to use a CPLD you should also implement the processor
in the gate array as this reduces the PCB wiring complexity considerably.

Trying to do all the filtering with an analog filter restricts the range
of loop response times to relatively small values degrading the
performance of the better OCXOs considerably.
Achieving time constants of 100 sec or more is somewhat
expensive/impractical using resistors and capacitors.
Some analog filtering is required but most of the long term filtering
should be done by the processor.

Layout and isolation of the DAC from processor created noise are critical.

Bruce

michael taylor wrote:

Michael

The analog circuitry for a sigma-delta DAC is attached.
The input is optically isolated using a high speed low jitter CMOS
optocoupler (Avago produce an equivalent device) to break low frequency
ground loops.
Similarly an RF transformer should be used to couple the OCXO output to
the Digital board breaking another potential low frequency ground loop.
The task of the microprocessor firmware is to generate the delta sigma 1
bit input data for the optocoupler.

Alternatively one of Analog devices chip scale transformer isolators
could be used.

Bruce

Bruce Griffiths wrote:

Michael

Attached is the circuit for a 1 bit phase detector.
HCMOS should be perfectly adequate given that the flipflop is allowed
several hundred millisec to settle before being read by the microprocessor.
An RF transformer isolated clock shaper should be used to shape the OCXO
output and avoid low frequency ground loops.
You probably want at least a 2 output distribution amplifier (unless
your OCXO has multiple isolated outputs eg FTS1200 OSA8607, some of the
Wenzel OCXOs, etc.) to allow the OCXO output to be used for other
applications as well.

The position of the divider output transition is adjusted by the control
algorithm with respect to the leading edge of the PPS signal so that the
D flipflop Q has a 50% chance of being 1 when read by the
microprocessor. The effective resolution is determined by the jitter of
the leading edge of the PPS pulse.

Bruce

Hi Bruce,

Fine, you don't like the words "far better performance"... okay ;-)
you do recognize the small advantage in noise but
gave no relevance to the other aspects namely the
lock acquisition, the fact that I can monitor the jitter over time
etc. (all of them were contained in my word "performance"
not just the noise).

you wrote,

Humm?! I did tried them, that's exactly what I said !!!
Note that I do have the hardware on a CPLD so schemes
can be done on type-compile-and-test basis without
soldering wires hi ;-)

Geeee, using a CPLD does not add complexity, it is just one chip
and it offers the commodity of being easily configured etc.
Also the power consumption is surely not an issue, if you
are not happy with the 50 to 100mA you may draw from 3.3v
just use a low power CPLD (like tha maxIIZ) and get
only 10 to 20mA.

On the comments about the filter and bandwidth I do agree
with you it would be good to have most of it digital
(doesn't need to be necessarily on a CPU... inside the CPLD
is the same) I do have versions with integration also
in digital and I'm still in the process of improving it.
I believe I may get rid off of some of the inconvenient
analog filtering, in the next VHDL iterations hi ;-)

One thing is puzzling me, if you suggest using a
single D flip-flop and want it simple as you say
I presume you have also to filter in analog ?!
So you end up with a slightly worst phase comparator
and the less convenient analog filter :-(

Or do you need to add a microcontroller and a DAC ?
If that is the case, there goes off your complexity issue
much higher than a simple CPLD.

Luis Cupido.
ct1dmk

Luis Cupido wrote:

Its not too difficult to add a couple of extra flipflops plus associated
delays to allow reasonably accurate estimation of noise if thats useful.

A theoretical understanding the performance tradeoffs can save a lot of
time and effort.

You have to keep in mind that not everyone on this list can or wants to
program a CPLD.

Where did you get that from??
No analog filtering of the D flipflop output is required.

Try reading up on how the radio astronomers digitise their noise like
signals.
You should also look at why a 1-2 bit ADC suffices for most GPS timing
receivers.

I've used plenty of CPLDs but see no reason to use one when it isnt
necessary.
If you want really high phase measurement resolution then the high noise
internal environment of a CPLD can add plenty of jitter and unwanted
crosstalk.
You are unlikely to ever achieve a jitter of 10picosec or less with a
standard CPLD whereas this is readily achieved using a single flipflop
or a wideband ADC used as a phase detector.

Bruce

Bruce,

The sentence in my perspective sounds a bit like this:
I've used plenty of TTL and CMOS but see no reason to use them
when I could fit them all on a CPLD.

I do understand that some may not want to get into this kind of
devices, however I see not much of a difference of
learning you way with microcontrollers, CPLDs or with any
digital IC's these days.

CPLDs in general do bring simplicity but do require learning
how to use them and for various reasons that may be undesirable
and be confused with a complexity issue while it is just a learning
issue.
Very good, I do respect the usage of a bunch of CMOS/TTL chips if
someone doesn't want to spend the
effort of learning how to use a CPLD. When it comes to use CPUs for
tasks better done by straight logic (and there are many examples
out there) then I think it is not the right option.
All understood so let's not discuss that any further.

Now you got me lost.

We were talking about a GPSDO, that is locking
an VCXO on the GPS time (1pps or else)
So by the end of it you need an analog
signal to control the voltage input of the VCXO. Right ?

Where you get that from ?
If not by filtering your flip-flop output
what else you have in between the 1pps and the VCXO ?
CPU's DAC's ????
if so how does your complexity arguments still apply ?

Luis Cupido

On Dec 12, 2007 7:33 AM, Luis Cupido cupido@mail.ua.pt wrote:

Bruce also alludes to the higher jitters of CPLD versus Advanced/High
Speed CMOS logic gates (AC or HC families).

This has to do with the programmable nature of CPLD / FPGA ICs as I
understand it.
Ref: http://www.febo.com/pipermail/time-nuts/2007-April/025299.html

-Michael

Bruce Griffiths wrote:

Yes!  I now feel inspired to go spin a design after studying all of
these messages in this
thread.  My only constraint is that the parts have to pass the "Digikey"
test, i.e. I have to
be able to order small quantities from Digikey, Mouser, or the like.
It's nearly impossible
for a hobbyist like me to get small quantities of more exotic parts.
The big distributors have
gotten better in the last decade about taking small orders, but still
often have minimum qty/piece
requirements that they won't waive.  Even worse are orderable, but
unobtainable parts -- Maxim
seems to have a huge library of such "virtual" chips that have lead
times of 1/2 year or more.

Scott

Luis Cupido wrote:

Some software, including a sigma delta DAC, the effect of which is no
different, in principle, than the filtering etc required by any of your
phase detector implementations.
The 1 bit phase error samples are processed in software (or hardware
depending on one's inclinations, expertise, etc) in a similar way that
samples from an N (>1) phase detector samples are, to produce a digital
output for a DAC which drives the OCXO EFC input. The only difference is
that a sigma delta DAC is used instead of a conventional DAC.

The interpretation of "complexity " depends on ones background and
experience.
The originator of the thread indicated that they had some microprocessor
software experience.

I was trying to tailor the design to the stated strengths of the
originator of the thread.

If one is trying to "squeeze" the ultimate in performance when using a
GPS receiver to discipline an OCXO, then carrier phase measurements
potentially offer much higher performance than can be achieved by using
the PPS output of a typical GPS timing receiver.
However only a few commercially available GPS receivers are suitable for
this application.
The GPS receiver oscillators all have to be phase locked to the OCXO
being disciplined.
This approach has been used in at least one commercially available GPSDOCXO.
In principle a GPS receiver has all the required measurement hardware,
so all that is required are suitable algorithms implemented in either
software running on a DSP, microprocessor, etc, or implemented in
hardware (CPLD etc).

Bruce

Scott Burris wrote:

Scott

I usually checkout the availability of parts in small quantity from such
sources, although which suppliers to check depends on your location.
Locally RS Components and Farnell are very good (they are also good
sources in Europe). I have a Digikey printed catalog with prices in my
local currency($NZ) (I have ordered a few things from them when I cant
easily get them locally). Linear Technologies on line ordering facility
works well for some of their more exotic parts and evaluation kits.

As far as I know Dallas/Maxim appears to be the only source of suitable
affordable programmable delay chips for this particular application.
In principle one could use a tapped chain of gates in a CPLD, however
continuous calibration of the delay is required (a delay locked loop
controlling the gate propagation delay by adjusting its power supply
voltage to compensate for the effect of temperature variations is one
technique). However unless the Dallas chips become hard to obtain its
probably best to leave this as a backup option.

What processor are you intending to use to decipher the sawtooth
correction messages from the GPS timing receiver?
You could use an inexpensive microprocessor dedicated to this simple task.
Another microprocessor can be used to discipline the OCXO.
Depending on your experience, this can be easier than using a single
microprocessor to do everything.

Bruce

Scott Burris wrote:

Scott

On checking the Mouser and Digikey websites the DS1020 series
programmable delay lines are non stock items.
However I can obtain the DS1020-25 locally from RS Components.
The D1020-15 would be preferable for use with an M12M GPS timing
receiver, however the DS1020-25 could be used.

Maybe we need to consider using a CPLD or another implementation (eg
ramp generator plus DAC (8bit) and comparator).
Analog Devices used to make a single chip implementation of the ramp
plus DAC and comparator programmable delay system.
However such devices need to be calibrated, preferably continuously.
The saving grace is that with a dedicated processor, there's plenty of
time and processing power to do this once a second (between successive
PPS pulses).

Calibration technique is simple:

1. Adjust the programmed delay so that the programmed delay is exactly 1
   (OCXO) clock period record the DAC data required to achieve this.

2. Adjust the programmed delay so that the programmed delay is exactly 2
   (OCXO) clock periods, record the DAC data required to achieve this.

3. calculate the OFFSET and GAIN parameters from the above data.

Of course such a scheme can be elaborated to include delays greater than
a couple clock periods and exponential averaging of results can be
employed to reduce the noise.
The calibration technique assumes that the delay is a linear function of
the DAC input.
A D flipflop plus some additional logic (synchroniser) can be used to
detect coincidence between the clock edge and the output of the delay
device.

Bruce

Bruce Griffiths wrote:

What about sending the 1PPS signal through a number of HC family gates
and using a mux
to select a tap -- is that better than using a CPLD? Hmm, probably the
delay varies too much from manufacturer to manufacturer
to make this work reliably.  Probably temperature sensitive too.

What kind of delay characteristics are needed?  I see some other delay
lines with 100ps
steps available, see:

http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=408-1127-ND

and put that through a mux?

Looks like some of the DS1020's are available through Maxim's e-commerce
site, but some have
a 15 week lead time, depending on the particular model.

I have experience with PICs, Atmel AVRs, and various ARM flavors, and
limited experience
with SOC processors in Xilinx FPGAs (Picoblaze and the like).  PICs and
AVRs are cheap, so no problem
dedicating one to this task.

Anyone have a list of GPS units which provide sawtooth correction data?
I have a few flavors of
Motorola products and a Trimble Lassen IQ laying around.  They all
provide 1PPS signals, but I bet
some don't have the necessary features.

Scott

Hi Michael,

Yes that may be true (but I did not test any of that...)
Well... with digital prog. logic devices that operate
at similar speed than HC and AC should be true yes.
On the fast CPLDs that run past 300MHz the jitter
should have scale down proportionally (I imagine)
but I have no clue if that is similar, better or still
worst than HC or AC.

Yeap... Nice thing to test
Hummm... I'm still thinking how to test such... :-)

Luis Cupido.
ct1dmk.

michael taylor wrote:

Ok. I understand now what you suggest.
Thanks for the explanation.

Luis Cupido.
ct1dmk.

Bruce Griffiths wrote:

Scott
Scott Burris wrote:

All of the above, however the major problems are that the individual
gate delay is too long and the designing a suitable multiplexer isnt easy.
I dont think that cascading 30 or more 1ns delay gates all in different
packages is going to work that well.
CPLDs have the advantage that to a first approximation all the gate
delays are identical.
However you have to force the configuration to interconnect them
appropriately software so as not to spoil the performance.

With an M12+T you need a minimum variable delay range of about 20ns or
so with a step size, accuracy and stability of better than 1ns
(resolution of sawtooth correction message) to avoid degrading performance.
Tom Clark suggested that the DS1020-15 with 150ps resolution is OK for
this receiver, however it needs to be calibrated over the delay range used.
Other receivers (particularly older ones) will need larger delay ranges.
The required delay range is around 0.5 to 1x  the receiver timing clock
period for the Motorola receivers.
Autocalibration techniques can be used to track the effects of
temperature and aging.

In principle this would work, the devil lies in the detail of the mux
design.
The mux delay needs to be independent of the selected tap.
The delay range provided by one of these devices is too small.
As a fallback option I have produced a draft schematic of a ramp style
delay generator with a resolution of 100ps and a range of 400ns or so.
The extended range allows calibration against a 10MHz OCXO derived clock
and should allow it to be used with most of the older Motorola Timing
receivers that provide sawtooth correction data.
Such calibrations can be interleaved between successive PPS pulses.
A 12 bit resolution DAC with a settling time (to 0.01%) of around
100millisec or so is required for this DAC.
It may be feasible to use a PWM DAC for this.

M12MT, M12+T, Trimble  Resolution-T all provide sawtooth correction data.

Bruce

On Dec 12, 2007 2:32 AM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

I was wondering if the Avago HCPL-9000 or Analog's ADUM1100 iCoupler
would be suitable alternatives to the HCPL-7100.

For the RF transformer I am considering a Coilcraft WB1-6(S)L
transformer to decouple the OCXO output.
http://www.coilcraft.com/wb_th.cfm

I want to do some more reading, but I think I'm might have some
questions about DAC input data (from the microprocessor).

Would there be any problems, or benefits to using AHC versus AC logic
family flipflops and the inverting Schmitt triggers?

In regards to the sawtooth correction, I am undecided. If I understand
correctly, even without not addressing it there should be an
improvement over existing public designs (Shera, Miller). If I
remember correctly, you were keen on a software/firmware based
sawtooth approach, if so that might be more flexible and cheaper than
fiddling with a uncalibrated DS1020 delay line.

Thank you,
Michael

Michael
michael taylor wrote:

Check the jitter, no jitter specs given for the iCouplers.
You may have to measure it on a sample.

The HCPL9000 should be fine but measure the jitter.
Circuit is actually reasonably tolerant to jitter as the low pass filter
averages such effects over many cycles.
If jitter proves a problem then if the micro or other logic generating
the sigma delta DAC bit-stream is clocked by the OCXO a D flipflop can
be used to retime the bitstream after the optocoupler/isolator reducing
the bit stream jitter to a few tens of picoseconds or so.

Probably OK although there appear to be no VSWR specs for these.

Whilst HC logic performance is adequate there is probably not too much
harm in using AHC or even AC as long as you use a ground plane together
with suitable layout techniques.
Metastability rates would go down by a large factor however the rate
with HC logic should be well below once every 1E10 years.

Depends on the entire system cost a single chip programmable delay plus
a D flipflop and little else should be cheaper than most high resolution
phase detector approaches.
As long as one can calibrate the DS1020 to improve its performance over
the datasheet specs. If it is sufficient to do this once (using a 5370
or equivalent) then the cost may be lower.
There are a lot of legacy devices/systems in use that actually require a
low jitter PPS pulse.

Most phase detectors with resolution, stability and accuracy better than
1ns (needs to be better than 500ps or so avoid significantly degrading
the quality of the correction) also require calibration unless one has a
suitable (2??) GHz clock (or equivalent) locked to the OCXO being
disciplined.
1ns accuracy and stability are perhaps easier to achieve when using a
sampled quadrature pair sine wave interpolator but even this requires
significant support logic to facilitate measuring harmonic content ,
quadrature error etc.

Bruce

Bruce Griffiths wrote:

Continuing the design discussions, anyone have opinions about powering
the HP 10811 oscillator?
I'm thinking that you want voltage regulators that are pretty quiet so
as to minimize jitter introduced
via the power supply.  To that end, I'm looking at a LT1761 for the +12v
OSC voltage and an LT3080
for the 24v heater supply.

In reading the 10811 manual, the heater and oscillator are isolated, yet
the example power supply ties
both together in a common ground.  That certainly would make things
simpler, as a 24VCT transformer
could be used, and +12 and +24 volts could be made pretty naturally that
way.

How important in a GPSDO application is it to keep these two sections
completely isolated?  I figure I would
either have to use a small HF transformer with a chopper circuit or a
separate 60hz transformer for the second
voltage.

Scott

On Dec 13, 2007 12:00 PM, Scott Burris slburris@gmail.com wrote:

You may want to read some related discussion from the archives, about
powering a Rb oscillator (different specs, similar concerns).
http://www.febo.com/pipermail/time-nuts/2007-October/027906.html

I didn't notice what the tempco is like for those LDO regulators, I
don't know if it is worth considering a (buried Zener) voltage
reference.

-Michael

You might try ebay for a +24 / +12 volt switching supply, problem/s solved.
I have bought them for as little as 3 bucks.
Phil

Bruce Griffiths wrote:

There is also a good programmable delay line from Dallas/MAXIM that is
less expensive (see http://www.maxim-ic.com/appnotes.cfm/an_pk/107).
Rick Hambly uses the DS1020-015 in his CNS Clock (see
http://www.cnssys.com). See slides 20, 26, 29 & 30 at
http://gpstime.com/files/tow-time2007.ppt for some details.

One comment on the Dallas/MAXIM DS1020 parts: we (Rick & I) found that
Motorola (in the M12 GPS receiver) and Dallas (in the delay line chip)
have a slightly different (~10%) definition for the nanosecond; it
appears to us that the Dallas/MAXIM definition is wrong, and the same
error shows up in many samples. Rick now uses the 150 psec/step Dallas
chip after finding that the ½ & 1 nsec versions had a scale error (see
slides 16-18 in ftp://ftp.cnssys.com/pub/PTTI/PTTI_2006.ppt which
represents slightly earlier work than presented at the 2007 TOW). The
"true" scale factor with the ~10% correction is contained in a look-up
table that converts the M12M binary sawtooth error output into the value
sent to the delay line.

Season's Greetings to all -- Tom

phil wrote:

Can you get switching power supplies with really low noise
characteristics?  The LT3080
is rated for 40uV of noise, and the LT1761 is rated for 20uV.  The 10811
manual
suggests less than 100uV of noise for the oscillator supply and less
than 30mV for the
heater.

I'm not saying you couldn't get down into the uV range with switchers
with some aggressive
filtering of some sort, but I'm not sure why one would go that route
over a linear supply,
which can hit those numbers with the right regulators.  Here I'm valuing
noise characteristics
over efficiency and size.

Scott

Scott
Scott Burris wrote:

How does the output noise of an LT1761 compare with the 5uV rms (100Hz
to 10KHz) output noise of the recommended LM723 regulator?

The important thing is to regulate the oscillator supply at the
oscillator supply pins and the oven supply at the oven supply pins.
With judicious application of Kelvin sensing the oven and oscillator
supply grounds can be connected together (or heater GND = -12V, Heater
supply = +12V) without significant interaction between the oven current
variations and the oscillator supply voltage. Similarly use Kelvin
sensing techniques (just use a conventional difference amplifier) to
control the EFC voltage between the EFC input and the common oscillator
EFC ground point within the OCXO.

Don't add noise unnecessarily unless you can live with the resultant
OCXO sidebands (or the cost/complexity of a suitable filter to remove
high frequency noise from the power supply).

Bruce

For low noise Zetex has a nice roll your own option, AN51

                              Steve

Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Scott
Scott Burris wrote:

How does the output noise of an LT1761 compare with the 5uV rms (100Hz
to 10KHz) output noise of the recommended LM723 regulator?

The important thing is to regulate the oscillator supply at the
oscillator supply pins and the oven supply at the oven supply pins.
With judicious application of Kelvin sensing the oven and oscillator
supply grounds can be connected together (or heater GND = -12V, Heater
supply = +12V) without significant interaction between the oven current
variations and the oscillator supply voltage. Similarly use Kelvin
sensing techniques (just use a conventional difference amplifier) to
control the EFC voltage between the EFC input and the common oscillator
EFC ground point within the OCXO.

Don't add noise unnecessarily unless you can live with the resultant
OCXO sidebands (or the cost/complexity of a suitable filter to remove
high frequency noise from the power supply).

Bruce

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steve heidmann wrote:

Steve

They "stole" that circuit topology from the Super regulator circuits
developed by Walt Jung among others.

One of the better sites with info on such regulators is:

http://sjostromaudio.com/joomla/index.php?option=com_content&task=view&id=26&Itemid=27
http://sjostromaudio.com/joomla/index.php?option=com_content&task=view&id=26&Itemid=27

He appears to have a good idea of what he's doing unlike most of the
fanatics in the audio community.

Bruce

On Fri, 14 Dec 2007, Bruce Griffiths wrote:

1. This is an unnecessarily complex design. You can achieve the same performance
   by cascading the "normal" regular with an integrated low noise regulator. I
   prefer Linear Technology ICs for this.

2. Bruce and others, you should really check your links before posting them. On
   this page was a link to get the full PDF of the schematic. When you click on
   that, you get a 404 not found plus you get a popup ad.  Worse still, if you
   click on the schematic to "enlarge" it, instead of getting the schematic
   you get a full page PORN ad.

73,

Jeffrey Pawlan  WA6KBL
Pawlan Communications

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Content preview:  On Fri, 14 Dec 2007, Bruce Griffiths wrote: > > One of the
better sites with info on such regulators is: > > http://sjostromaudio.com/joomla/index.php?option=com_content&task=view&id=26&Itemid=27

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On Dec 13, 2007 6:24 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

http://waltjung.org/Regs.html

Bruce can post all the porn links he wants.  I'm already going to have to
install a new hard drive to archive all the useful schematics and design
notes he's been contributing!  Might as well fill up the remaining space
with SOMETHING.

In case the message isn't clear enough, I really appreciate these pointers,
especially low-noise supply ideas.  It's surprising how few off-the-shelf
regulator ICs these days are even as good as the old uA723 from the 1970s.

-- john, KE5FX

John Miles wrote:

Actually you cant, which is the  point.

I usually do check the links, the extraneous link to a porn site is
relatively recent "feature" as it wasn't there a few days ago.
I've even seen such transient links appear on the Oscilloquartz site.
For some reason this problem appears to be more prevalent with European
sites, however this may be an indavertent selection effect.

Bruce

Have just checked I dont see any PORN site, the problem may be at your end.
However I do get an extraneous nonporn  popup window
Will try to locate reliable links to the actual pdf files for these
circuits.

Failing that I've actually downloaded them and can send them to anyone
who wants them.

Bruce

He has "ultra high performance rectifier bridges".  Sounds like snake oil to me.

Matt

On Dec 13, 2007 5:57 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Matt Ettus wrote:

Try looking at the circuit  before commenting.
Different culture express themselves in slightly different ways, its
best to study the actual circuit and think about what the designer may
mean by the term.
You will find that he actually uses fast recovery diodes with snubbers
to reduce RFI.
You also have to bear in mind the market into which he is selling these
devices, they expect some hype of this sort.

Bruce

On Dec 13, 2007 6:15 PM, Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

I did.

Can you explain to me the use of fast recovery diodes if you are going
to put capacitors across them?

The market he is selling into expects snake oil.

Matt

On Fri, 14 Dec 2007, Bruce Griffiths wrote:

The problem is definitely not in my Sun workstation which is fortunately running
unix so it is impervious to all the bad people out there. But I have noticed
that sites target the locale of the IP address that is trying to access the URL.

Then depending on the laws of that country and also the whims of the site
owner, one will get very different things. So from New Zealand you are seeing
one thing and from Calif I am seeing another. It is referred to as targeted ads.

I saw that previously in another European site used by amateur radio operators.

Jeffrey

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Content preview:  On Fri, 14 Dec 2007, Bruce Griffiths wrote: > Have just checked
I dont see any P... site, the problem may be at your end. > However I do
get an extraneous nonporn popup window > Will try to locate reliable links
to the actual pdf files for these > circuits. > > Failing that I've actually
downloaded them and can send them to anyone > who wants them. > > Bruce [...]

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Matt
Matt Ettus wrote:

Even with the snubber networks the reverse conduction time of the fast
recovery diodes is considerably shorter than when a standard recovery
rectifier is used.
Its the high current pulse during rectifier reverse recovery time that
generates the RFI when standard recovery rectifiers are used.
The transformer leakage inductance also exacerbates the situation
especially if a shunt capacitor and/or snubber isnt placed across the
rectifier AC input close to the rectifier.
As long as the reverse recovery isnt too abrupt fast recovery diodes
generate less RFI (at least at low RF frequencies) than standard
recovery rectifiers even when the input frequency is relatively low
(50Hz, 60Hz etc).

The effect of the additional capacitors and snubbers (particularly the
one across the rectifier AC input) is noticeable even when using
standard recovery diodes.
You can detect the RFI generated by unsnubbed rectifiers with an AM
radio at surprisingly large distances, when properly snubbed you have to
get much closer.

Thats why you have to make allowances.

Bruce

We even use snubbers across Shottky and FRED rectifiers, in spite of what
the vendor's litterature claims.
Anything that is non linear in series with a magnetic structure (does not
have to be a transformer, a trace or wire long enough would do) is a
potential source of ringing and noise.

Didier KO4BB

I can see using fast-recovery diodes if you want to rectify the output of a
switching supply, to limit the losses.  Ordinary 1N400x diodes start to run
very hot above a few kHz.  In a switcher, it would be reasonable to use
fast-recovery diodes with capacitors to control both EMI and loss.

But yeah, it's hard to see the point in a 50/60-Hz supply.  Schottkys have
less forward voltage drop, I guess, so maybe the idea is to use smaller
diodes/heat sinks for a given supply current.

-- john, KE5FX

On Thursday 13 December 2007 09:40:39 pm Jeffrey Pawlan wrote:

For stuff like this, it matters less what operating system you use than what
web browser you use -- and they all have had vulnerabilities so make sure you
keep it updated.

You can also be attacked via the DNS server you use -- in which case your
operating system is completely irrelevant.

Don't know about this specific case, but it often has nothing to do with
the "whims of the site owner". If they sell advertising space through a third
party, they are at least partly at the mercy of who the third party resells
the ad space to. Even sites that sell through Google Ads get nailed with bad
stuff once in a while because people manage to sneak stuff past them.

• Bob