Hi All, I'm trying to make a custom OOT block for rfnoc4. I already went through the synthesis of the stock rfnoc firmware, as well as the gain example: all works well on my x300. I added some custom logic in the gain example's verilog and I am quite satisfied with the results. The next step for me is to integrate a more complex design that includes CORDICs, FFTs and other IPs from Xilinx. To do that, I plan to develop a block design in Vivado and pass it to the rfnoc infrastructure. I'd like to know if you attempted this workflow and if there is a guide of some sort for getting started. Right now, I am quite lost. 1. The IPs that Vivado generate have an AXI interface, I suspect I cannot directly reproduce the steps to implement the gain block. 2. Once I have my top module, how do I integrate it in the rfnoc workflow? A basic example of the gain block (or even an empty pass-through block) implemented via the Vivado block design technique would be really appreciated. I work for a non-profit research institution (Caltech); all my results will be available under some open-source license. My plan is also to release a guide that documents how I developed the firmware. Thanks, Lorenzo

1. The IPs that Vivado generate have an AXI interface, I suspect I
cannot directly reproduce the steps to implement the gain block.
2. Once I have my top module, how do I integrate it in the rfnoc
workflow?

Hi Lorenzo, I am not much experienced with RFNoC workflow, but I have added custom logic into RFNoC. While doing that, I analyzed the gain example. In the gain example, there are 3 different options; HDL_IP, IN_TREE_IP and OUT_OF_TREE_IP. For the OUT_OF_TREE_IP option, it uses Xilinx Complex multiplier IP and they only used its ."xci" file. I have also added DDS Xilinx IP by using its ".xci" file. So, if you want to add Xilinx IP, all you need is the ".xci" file of that IP. Xilinx IPs have an AXI Interface as a standard, but it does not mean you cannot use it in RFNoC. RFNoC has ctrl_ports which you can create registers and control from the host and has payload ports which transfers ADC and DAC datas. Therefore; you have all you need to add any design in Verilog. You can add any IP in verilog by instantiation (i.e., Complex Multiplier IP in gain example) and control that IP with registers and your own algorithms. For the block design approach, I do not know how to add it into RFNoC. As I have seen it, the RFNoC workflow does not work that way. Therefore; that might be easier to use verilog for algorithms and ".xci" file for IPs. Yasir Minutolo, Lorenzo <minutolo@caltech.edu>, 17 Ağu 2022 Çar, 02:34 tarihinde şunu yazdı: > Hi All, > I'm trying to make a custom OOT block for rfnoc4. > I already went through the synthesis of the stock rfnoc firmware, as well > as the gain example: all works well on my x300. > I added some custom logic in the gain example's verilog and I am quite > satisfied with the results. > > The next step for me is to integrate a more complex design that includes > CORDICs, FFTs and other IPs from Xilinx. > To do that, I plan to develop a block design in Vivado and pass it to the > rfnoc infrastructure. > > I'd like to know if you attempted this workflow and if there is a guide of > some sort for getting started. > > Right now, I am quite lost. > > 1. The IPs that Vivado generate have an AXI interface, I suspect I > cannot directly reproduce the steps to implement the gain block. > 2. Once I have my top module, how do I integrate it in the rfnoc > workflow? > > A basic example of the gain block (or even an empty pass-through block) > implemented via the Vivado block design technique would be really > appreciated. > > I work for a non-profit research institution (Caltech); all my results > will be available under some open-source license. My plan is also to > release a guide that documents how I developed the firmware. > > Thanks, > Lorenzo > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >

1. The IPs that Vivado generate have an AXI interface, I suspect I
cannot directly reproduce the steps to implement the gain block.
2. Once I have my top module, how do I integrate it in the rfnoc
workflow?

Hi Lorenzo, I don't know of any examples of RFNoC blocks that use block designs, but in principle using a BD is similar to using any other Xilinx IP. If you search for *.bd files or *_bd.tcl in the UHD repository, you'll find several examples of IP that is pulled into the USRP code as a block design. When you build the IP for a BD, you get synthesizable Verilog code. You can then instantiate the top-level Verilog file for the BD into your RFNoC block's HDL code. As an example, maybe look at fpga/usrp3/top/x300/ip/axi_intercon_2x64_128_bd/ Notice in Makefile.inc how it calls BUILD_VIVADO_BD to build the BD and generate the HDL files. Wade On Wed, Aug 17, 2022 at 8:45 AM Yasir Özçalık <simultaneous11@gmail.com> wrote: > Hi Lorenzo, > I am not much experienced with RFNoC workflow, but I have added custom > logic into RFNoC. While doing that, I analyzed the gain example. In the > gain example, there are 3 different options; HDL_IP, IN_TREE_IP and > OUT_OF_TREE_IP. For the OUT_OF_TREE_IP option, it uses Xilinx Complex > multiplier IP and they only used its ."xci" file. I have also added DDS > Xilinx IP by using its ".xci" file. So, if you want to add Xilinx IP, all > you need is the ".xci" file of that IP. > > Xilinx IPs have an AXI Interface as a standard, but it does not mean you > cannot use it in RFNoC. RFNoC has ctrl_ports which you can create registers > and control from the host and has payload ports which transfers ADC and DAC > datas. Therefore; you have all you need to add any design in Verilog. You > can add any IP in verilog by instantiation (i.e., Complex Multiplier IP in > gain example) and control that IP with registers and your own algorithms. > > For the block design approach, I do not know how to add it into RFNoC. As > I have seen it, the RFNoC workflow does not work that way. Therefore; that > might be easier to use verilog for algorithms and ".xci" file for IPs. > > Yasir > > Minutolo, Lorenzo <minutolo@caltech.edu>, 17 Ağu 2022 Çar, 02:34 > tarihinde şunu yazdı: > >> Hi All, >> I'm trying to make a custom OOT block for rfnoc4. >> I already went through the synthesis of the stock rfnoc firmware, as well >> as the gain example: all works well on my x300. >> I added some custom logic in the gain example's verilog and I am quite >> satisfied with the results. >> >> The next step for me is to integrate a more complex design that includes >> CORDICs, FFTs and other IPs from Xilinx. >> To do that, I plan to develop a block design in Vivado and pass it to the >> rfnoc infrastructure. >> >> I'd like to know if you attempted this workflow and if there is a guide >> of some sort for getting started. >> >> Right now, I am quite lost. >> >> 1. The IPs that Vivado generate have an AXI interface, I suspect I >> cannot directly reproduce the steps to implement the gain block. >> 2. Once I have my top module, how do I integrate it in the rfnoc >> workflow? >> >> A basic example of the gain block (or even an empty pass-through block) >> implemented via the Vivado block design technique would be really >> appreciated. >> >> I work for a non-profit research institution (Caltech); all my results >> will be available under some open-source license. My plan is also to >> release a guide that documents how I developed the firmware. >> >> Thanks, >> Lorenzo >> >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-leave@lists.ettus.com >> > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >