Bruce,
Can you please provide some references to phase noise problems/performance
of the passive components you mention?
Pete Rawson
On Fri, Mar 02, 2007 at 04:02:39AM +1300, Dr Bruce Griffiths wrote:
Its not just the temperature coefficients, real inductors and capacitors
have inherent phase noise.
Silver mica capacitors can be very bad as are ferrite core inductors.
Mylar capacitors are good as are NP0/C0G ceramics and X7R is acceptable
for low impedance coupling and decoupling.
Air core and iron powder core inductors are good.
This is intriguing, and something I'd really not thought about.
Care to elaborate as to magnitudes and nature of such random
presumptive variations in capacitance/inductance - does the sideband
energy induced by these effects roll off with rapidly with increasing
frequency or extend up to tens of kHz or MHz ? What causes them ?
Are they actual small random changes in capacitance or inductance or a
more complex non-linear physical effect involving energy storage
mechanisms ?
On another point I can certainly see the issues with long time
constant phase shifts through narrow crystal bandpass filters with hi Q
resonances caused by thermal shifts in component values, but do real
world crystal "clean-up" filters actually contribute significant short
term (say 1 Hz and above) phase modulation ? Many RF applications
care deeply about absolutely minimized levels of energy say 1 Hz to 100
kHz or more from the carrier but could care less about absolute phase
relative to a reference (or Allen Deviation measured with taus in
hours). Thus the thermal changes aren't important, but modulation at
much higher frequencies is. And yes I can see that vibration makes
crystal clean up filters a problem... at least for systems subject to
enough to cause microphonic effects.
I had never thought about relative performance issues of using a
VCXO locked with a really narrow band PLL to a lower frequency reference
versus a multiplier with a narrow band cleanup filter at the output...
other than to realize that unless one uses a more complex PLL design
really narrow band loops implemented extremely straightforwardly
(perhaps to the point of idiocy) require the higher frequency VCXO to be
accurately on frequency within the low pass bandwidth else the loop
won't capture. This gets a bit dicey if one is talking 1 Hz or less at
100 MHz.
And of course if the loop bandwidth is wider, then the phase
noise in that wider bandwidth is more or less the phase noise of the
reference times the multiplying factor and not just the phase noise of
the VXCO.. But yes, these days a loop can be designed to handle this
capture issue with a little more effort...
--
Dave Emery N1PRE, die@dieconsulting.com DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."
Pete wrote:
Bruce,
Can you please provide some references to phase noise problems/performance
of the passive components you mention?
Pete Rawson
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Pete
Try
http://tf.nist.gov/timefreq/general/pdf/1244.pdf
This is an update on a brief mention in a paper published about 20 years
earlier which contained few details, other than a cryptic statement that
a large proportion of silver mica capacitors had large phase noise.
Bruce
David I. Emery wrote:
On Fri, Mar 02, 2007 at 04:02:39AM +1300, Dr Bruce Griffiths wrote:
Its not just the temperature coefficients, real inductors and capacitors
have inherent phase noise.
Silver mica capacitors can be very bad as are ferrite core inductors.
Mylar capacitors are good as are NP0/C0G ceramics and X7R is acceptable
for low impedance coupling and decoupling.
Air core and iron powder core inductors are good.
This is intriguing, and something I'd really not thought about.
Care to elaborate as to magnitudes and nature of such random
presumptive variations in capacitance/inductance - does the sideband
energy induced by these effects roll off with rapidly with increasing
frequency or extend up to tens of kHz or MHz ? What causes them ?
Are they actual small random changes in capacitance or inductance or a
more complex non-linear physical effect involving energy storage
mechanisms ?
On another point I can certainly see the issues with long time
constant phase shifts through narrow crystal bandpass filters with hi Q
resonances caused by thermal shifts in component values, but do real
world crystal "clean-up" filters actually contribute significant short
term (say 1 Hz and above) phase modulation ? Many RF applications
care deeply about absolutely minimized levels of energy say 1 Hz to 100
kHz or more from the carrier but could care less about absolute phase
relative to a reference (or Allen Deviation measured with taus in
hours). Thus the thermal changes aren't important, but modulation at
much higher frequencies is. And yes I can see that vibration makes
crystal clean up filters a problem... at least for systems subject to
enough to cause microphonic effects.
I had never thought about relative performance issues of using a
VCXO locked with a really narrow band PLL to a lower frequency reference
versus a multiplier with a narrow band cleanup filter at the output...
other than to realize that unless one uses a more complex PLL design
really narrow band loops implemented extremely straightforwardly
(perhaps to the point of idiocy) require the higher frequency VCXO to be
accurately on frequency within the low pass bandwidth else the loop
won't capture. This gets a bit dicey if one is talking 1 Hz or less at
100 MHz.
And of course if the loop bandwidth is wider, then the phase
noise in that wider bandwidth is more or less the phase noise of the
reference times the multiplying factor and not just the phase noise of
the VXCO.. But yes, these days a loop can be designed to handle this
capture issue with a little more effort...
David
Even vibration isolated isothermal constant temperature crystals exhibit
phase noise.
The components exhibit fluctuations in reactance.
The additional phase noise decreases with frequency offset, but if you
are multiplying by 100x or so, even the phase noise at an offset of
100Hz at the reference frequency may be a problem see:
http://tf.nist.gov/timefreq/general/pdf/1244.pdf
Bruce
Ulrich Bangert wrote:
Hi foks,
I want to put forward a similar but slightly different question:
Suppose I need an clock running at around 50 Mhz for an DDS. Because of
the DDS it need not be exactly 50 MHz, can be 52 or 54 MHz too.
Basically this clock shall be derived from a 10 MHz source (OCXO,
Rubidium...) The OUTPUT of the DDS is to be used as an frequency
standard, with the DDS being an complete digital steering circuit.
If I have the choice to use
a) an harmonic X5 multiplier for the 10 MHz signal
or
b) a 54 MHz VCXO with the following specs: 0.8 ps RMS jitter, noise
floor -145 db @ 100 kHz offset phase locked to the 10 MHz
what is the prefered solution? Or is the answer dependent on what I plan
to use the frequency standard for?
TIA
Ulrich Bangert, DF6JB
Ulrich
Whilst in general the answer does depend on the application the
following observations concerning the phase noise floor of the ~50MHz
signal may be useful.
With a state of the art OCXO with a phase noise floor of less than
-170dBc/Hz multiplying by 5 with a low phase noise multiplier will raise
the phase noise floor to around -156dBc/Hz somewhat less than that of
your proposed VCXO. However if your 10MHz standard has a phase noise
floor higher than -160dBc/Hz the 54MHz VCXO will have a lower phase
noise floor.
The phase noise at offsets closer to the carrier will usually be less
when multiplying a low noise 10MHz reference than for a higher VCXO.
If you only need to adjust the frequency by a few ppm then one can
cleanup the spurs and phase noise of a DDS reducing them to very low
levels by using a cascaded mix and divide technique like that in:
http://www.karlquist.com/FCS95.pdf
With such a circuit you can achieve a phase noise floor (if you use
appropriate dividers especially in the last stage) approaching that of a
good OCXO.
With this technique there is no need to use a ~ 50MHz reference for the
DDS if all you want is a corrected 10MHz signal.
Bruce
Bruce,
thank you for your help! Since it is not known a priori what kind of
source will serve for the 10 MHz input I must take into account that it
is not the absolute state of art. Since the VCXO solution is not far
away from state of the art I consider it the better general choice.
I know Rick's papers about synthesizers since a few years and I have
been impressed by them a lot. Until now I have been thinking that the
complexity with the additional mixers, buffers and filters is to high
but perhaps I am going to re-think it. The private lessons that I
received from you concerning low noise amplification make at least the
buffer part a handable task.
Best regards
Ulrich Bangert
-----Ursprüngliche Nachricht-----
Von: time-nuts-bounces@febo.com
[mailto:time-nuts-bounces@febo.com] Im Auftrag von Dr Bruce Griffiths
Gesendet: Freitag, 2. März 2007 00:23
An: Discussion of precise time and frequency measurement
Betreff: Re: [time-nuts] Low noise frequency multiplication
Ulrich Bangert wrote:
Hi foks,
I want to put forward a similar but slightly different question:
Suppose I need an clock running at around 50 Mhz for an
DDS. Because
of the DDS it need not be exactly 50 MHz, can be 52 or 54 MHz too.
Basically this clock shall be derived from a 10 MHz source (OCXO,
Rubidium...) The OUTPUT of the DDS is to be used as an frequency
standard, with the DDS being an complete digital steering
circuit. If
I have the choice to use
a) an harmonic X5 multiplier for the 10 MHz signal
or
b) a 54 MHz VCXO with the following specs: 0.8 ps RMS jitter, noise
floor -145 db @ 100 kHz offset phase locked to the 10 MHz
what is the prefered solution? Or is the answer dependent on what I
plan to use the frequency standard for?
TIA
Ulrich Bangert, DF6JB
Ulrich
Whilst in general the answer does depend on the application the
following observations concerning the phase noise floor of the ~50MHz
signal may be useful.
With a state of the art OCXO with a phase noise floor of less than
-170dBc/Hz multiplying by 5 with a low phase noise multiplier
will raise
the phase noise floor to around -156dBc/Hz somewhat less than that of
your proposed VCXO. However if your 10MHz standard has a phase noise
floor higher than -160dBc/Hz the 54MHz VCXO will have a lower phase
noise floor.
The phase noise at offsets closer to the carrier will usually be less
when multiplying a low noise 10MHz reference than for a higher VCXO.
If you only need to adjust the frequency by a few ppm then one can
cleanup the spurs and phase noise of a DDS reducing them to very low
levels by using a cascaded mix and divide technique like that in:
http://www.karlquist.com/FCS95.pdf
With such a circuit you can achieve a phase noise floor (if you use
appropriate dividers especially in the last stage) approaching that of a
good OCXO.
With this technique there is no need to use a ~ 50MHz reference for the
DDS if all you want is a corrected 10MHz signal.
Bruce
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