Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
richard@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know anything about building digital
hardware any more (40 years of experience wasted). Nobody cares about look
ahead carry, etc.
Is that really true? Or perhaps, what fraction of the digital design space
does it apply to?
How fast was your counter running? How fast would it run? Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster? Could you buy a
faster chip? How much more could you get with tricky logic?
I agree that modern tools and parts have allowed a lot more people to build
digital circuits.
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Hi
On Jun 5, 2015, at 11:19 PM, Hal Murray hmurray@megapathdsl.net wrote:
richard@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know anything about building digital
hardware any more (40 years of experience wasted). Nobody cares about look
ahead carry, etc.
Is that really true?
Yes, it’s really true.
Or perhaps, what fraction of the digital design space
does it apply to?
The portion that does not take the design directly to an ASIC. (at
least in industry). Essentially the only thing done with discrete logic
these days are minor i/o chores.
How fast was your counter running?
How fast would it run?
That depends entirely on which FPGA or CPLD you buy. An old 100 MHz part will not
go as fast as a 800 MHz part. In this case speed is the toggle rate on the counter.
Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster?
Bought a faster FPGA or gone to an ASIC.
Could you buy a
faster chip?
For enough money there’s always a faster chip :)
How much more could you get with tricky logic?
The days of “tricky logic” ( = stuff the software does not understand) are now
the days of “hand place (route) the gates in the FPGA”. It’s routing delay that
gets you before gate speed in most cases. The software routers have gotten
awfully good ….
I agree that modern tools and parts have allowed a lot more people to build
digital circuits.
They did that only after they had been allowing mass conversion of designs over
to silicon for about two decades. The tools you see today are nothing like what
you had to use in the early 1990’s.
The other thing that the design software has done is that it’s forced people to
face up to timing constraints. Just as in the semiconductor industry, there is now
a “process spec” that is used to constrain the design. If it passes when fully
constrained and checked, it will work in production. No more blue wires. No more
“oops!” re-spins on $20,000 pc boards.
Bob
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The counter only had to run at ~50 MHz, on account of our
mode locked laser ran at that frequency. I don't remember
what the CPLD was rated at.
Rick
On 6/5/2015 8:19 PM, Hal Murray wrote:
richard@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know anything about building digital
hardware any more (40 years of experience wasted). Nobody cares about look
ahead carry, etc.
Is that really true? Or perhaps, what fraction of the digital design space
does it apply to?
How fast was your counter running? How fast would it run? Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster? Could you buy a
faster chip? How much more could you get with tricky logic?
I agree that modern tools and parts have allowed a lot more people to build
digital circuits.
Hi
Here’s an example:
http://parts.arrow.com/item/detail/arrow-development-tools/bemicromax10#pg2e
https://www.altera.com/products/fpga/max-series/max-10/overview.highResolutionDisplay.html
There are other outfits that make similar parts that are at least as good. This is considered a
low end chip right now. The part on the demo board is a mid point for the part size wise.
It will run 400 MHz clocks without much bother at all. It also is quite happy doing multiple modulo
divides to take those clocks down to multiple 1 pps outputs and have a load function on the
counter. You have enough room to use them as time tags on inputs to the FPGA and store a few
hours worth of data in memory.
Can you do better with a faster part? sure can. Can you find cheaper parts? yes again. Is there
a competitor’s part that will do it cheaper / faster / easier (pick one) - most certainly.
If you can enter a schematic into free software, you can design a pps divider with a part like this.
No need to learn a programming language to work with one. The process is roughly the same as
learning a new pcb layout tool. Yes it runs on Linux and on Windows.
I can’t buy the parts on the demo board for what they sell the board for. I can’t buy an 8 -10
layer board that size in single piece for what they sell the demo board for. I can’t get it assembled
(BGA’s …) in one piece for what they sell the demo board for. I also can’t do multiples
of that counter with discrete logic on a board that size. I also can’t buy all the chips that a
counter that fast going that low would require (plus the board) for what the demo board
costs. Bottom line, to use them, just buy them already on a board and mount that on
whatever you are doing.
No I’m not trying to sell you that demo board. I’m also not trying to convince you that there is one
and only one family of parts that are worth using. The point is - the world started going over to
FPGA’s in the mid 1980’s. Discrete logic design started to die out with ASIC’s in the early 1970’s.
For large scale stuff it was dead by the end of the 1970’s. Forty years later, there are very few
places (other than i/o) that discrete gates get used.
The world has changed a lot since the 1970’s. Design any UART’s with discrete logic since about 1971?
Bob
On Jun 5, 2015, at 11:19 PM, Hal Murray hmurray@megapathdsl.net wrote:
richard@karlquist.com said:
I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
timebase. It was great because you just write a 17 bit counter in VHDL and
there it is. You don't have to know anything about building digital
hardware any more (40 years of experience wasted). Nobody cares about look
ahead carry, etc.
Is that really true? Or perhaps, what fraction of the digital design space
does it apply to?
How fast was your counter running? How fast would it run? Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster? Could you buy a
faster chip? How much more could you get with tricky logic?
I agree that modern tools and parts have allowed a lot more people to build
digital circuits.
--
These are my opinions. I hate spam.
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On Sat, 6 Jun 2015 09:52:11 -0400
Bob Camp kb8tq@n1k.org wrote:
Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster?
Bought a faster FPGA or gone to an ASIC.
Could you buy a
faster chip?
For enough money there’s always a faster chip :)
Even if it is OT, to give this a little economic perspective:
Today, an ASIC starts to be cheaper than an FPGA solution at production
volumes somewhere between 1000 and 10'000 pieces (in total).
If you have working (synchronous) VHDL code, going ASIC is pretty
straight forward and is mostly automatic. There are several fabs
in Europe and Asia that offer node sizes between 180nm and 35nm
for even very small runs and help you to convert your FPGA code
to proper ASIC designs.
A simple ASIC project is cheap enough, that some universities offer
courses where students (in a master course) design their own chips,
let them produce and measure their performance later, all cost covered
by the university. (If i remember correctly, the cost was around 10kUSD
per design and for 20 dies, half of them in QFP, half as nacked die)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
Hi
Last time I saw university multi project wafer prices, the cost was around $5K for a
run on a “not state of the art” fab process. That included absolutely nothing
in the way of design assistance. It was strictly “we fab what you told us to do”. The
“run date” for the chips was also a bit vague. They used space on other design runs, so
you got about a 3 month window on when your parts might run. Eventually you got back
a waffle pack with some die to go wire bond up.
Often the trick was to take the work of several students and put in on a single chip. The
hope was that nothing pathogenic happened in any of the designs to render the
whole thing useless.
The gotcha on ASIC’s os (of course) the running cost of this stuff. If you are using a bunch
of parts is’t not to bad. If not, the phone call every 4 years or so about “you need to
buy a new mask set for $XXX,XXX” gets a bit old. For a state of the art process add
at least one more X to that number.
Coming back to timing. Once you go to an ASIC, the ability to optimize for low
jitter / good ADEV (or whatever) comes into the picture. There is no reason why
there should be any worse performance on the ASIC than on any logic family
you can find. All of the previous caveats about phase noise floors go away. That’s
not to say that things like crosstalk between two pads that are 0.05 mm apart suddenly
vanishes. You still have to take care of the i/o part of the design.
Bob
On Jun 6, 2015, at 1:49 PM, Attila Kinali attila@kinali.ch wrote:
On Sat, 6 Jun 2015 09:52:11 -0400
Bob Camp kb8tq@n1k.org wrote:
Was it a simple
counter or was there enable/up/down/load type gating involved?
What would you have done if you needed to run a bit faster?
Bought a faster FPGA or gone to an ASIC.
Could you buy a
faster chip?
For enough money there’s always a faster chip :)
Even if it is OT, to give this a little economic perspective:
Today, an ASIC starts to be cheaper than an FPGA solution at production
volumes somewhere between 1000 and 10'000 pieces (in total).
If you have working (synchronous) VHDL code, going ASIC is pretty
straight forward and is mostly automatic. There are several fabs
in Europe and Asia that offer node sizes between 180nm and 35nm
for even very small runs and help you to convert your FPGA code
to proper ASIC designs.
A simple ASIC project is cheap enough, that some universities offer
courses where students (in a master course) design their own chips,
let them produce and measure their performance later, all cost covered
by the university. (If i remember correctly, the cost was around 10kUSD
per design and for 20 dies, half of them in QFP, half as nacked die)
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson
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My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... .
Bruce pointed me to Rubiola's paper http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf, and while I'm sure the lambda divider is excellent, there's a definite problem of needing to re-square the output after every stage if you want a multi-stage design. This makes me wonder if you'd end up adding enough additional jitter/phase noise to more than counteract the benefit of the lambda divider (which produces a stepped triangle wave). TANSTAAFL seems to apply here.
My biggest concern is that if I build a multi-stage divider (*) using a single CPLD or FPGA, I could end up with cross-talk problems similar that encountered with multi-gate logic packages. I don't think it makes sense to use a CPLD if you need to use a separate package for each stage.
I'm also a bit concerned by Bob Camp's comment:
they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS
which suggests that it will be (at least 10dB) worse than my existing design :(
I guess that it might work if the output were re-synched to the input using external D-flops after the main grunt work is done in a CPLD/FPGA.
I'm also a bothered by the findings in http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf which indicate that the lowest noise devices tested were the Altera Max 3000 series which Altera dsecribe as "Mature" so may be at risk of obsolescence
Thanks to all for the discussion to date.
(*) similar to my previous effort made with 74AC logic.
Thanks again
Dave
Hi
As always, the real answer is “that depends”.
If you are dividing to 1 pps from 10 MHz, the CPLD or FPGA is a fine answer to the question. It will give you some cool bells and whistles (like sync and advance / retard) without adding anything to the budget. If you wish to re-sync the output with a single gate D-FF running on the “wrong edge” of the 10 MHz, that’s easily done and it adds virtually nothing to the board space or cost.
If you are building a low noise PLL and going from 160 MHz down to a 40 MHz analog phase detector (with a floor of -170 dbc/ Hz), the CLPD or FPGA isn’t a good choice. You can do the complete divide with a single package part and get lower noise.
The board with the 160 MHz PLL on it is going to be a single purpose layout and it will live it’s life doing one thing. The board with the 1 pps
divider might get re-purposed to do a variety of things. A “universal” FPGA board with some basic timing stuff (connectors / re-sync flip flops / input gates) on it might be a very useful thing to have around …..
On Jun 7, 2015, at 6:23 AM, David C. Partridge david.partridge@perdrix.co.uk wrote:
My reading so far of what's been said in this thread is that you might get good results using a CPLD/FPGA as a divider but ... .
Bruce pointed me to Rubiola's paper http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf, and while I'm sure the lambda divider is excellent, there's a definite problem of needing to re-square the output after every stage if you want a multi-stage design. This makes me wonder if you'd end up adding enough additional jitter/phase noise to more than counteract the benefit of the lambda divider (which produces a stepped triangle wave). TANSTAAFL seems to apply here.
My biggest concern is that if I build a multi-stage divider (*) using a single CPLD or FPGA, I could end up with cross-talk problems similar that encountered with multi-gate logic packages.
Internal cross talk on FPGA’s and CPLD’s is pretty much a non-issue. That assumes that the board is properly laid out and the supplies are
well bypassed. Input and output cross talk can be reduced (but not always eliminated) by running differential inputs and putting “threat” signals on different i/o banks from each other.
The “properly laid out” constraint with a FPGA / CPLD forces you to a > 2 layer board pretty fast. Depending on the density and a few other things you may be past 6 layers. Yes that costs money.
Bob
I don't think it makes sense to use a CPLD if you need to use a separate package for each stage.
I'm also a bit concerned by Bob Camp's comment:
they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz you could expect under similar conditions with something like AC or faster CMOS
which suggests that it will be (at least 10dB) worse than my existing design :(
I guess that it might work if the output were re-synched to the input using external D-flops after the main grunt work is done in a CPLD/FPGA.
I'm also a bothered by the findings in http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf which indicate that the lowest noise devices tested were the Altera Max 3000 series which Altera dsecribe as "Mature" so may be at risk of obsolescence
Thanks to all for the discussion to date.
(*) similar to my previous effort made with 74AC logic.
Thanks again
Dave
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On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:
My reading so far of what's been said in this thread is that you might
get good results using a CPLD/FPGA as a divider but ... .
..
..
..
Thanks again Dave
Is this going to be an "open source" project, or something you buy ?
CFO
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I'm up for either ... My thoughts are to try it out on a development board and if it works, maybe build a few for possible sale, and also release Gerbers and VHDL files.
Regards,
David Partridge
-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@febo.com] On Behalf Of cfo
Sent: 08 June 2015 15:09
To: time-nuts@febo.com
Subject: Re: [time-nuts] Using CPLD/FPGA or similar for frequency divider
On Sun, 07 Jun 2015 11:23:40 +0100, David C. Partridge wrote:
My reading so far of what's been said in this thread is that you might
get good results using a CPLD/FPGA as a divider but ... .
..
..
..
Thanks again Dave
Is this going to be an "open source" project, or something you buy ?
CFO
--
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