System: CentOS 8 using Anaconda3 with the conda-forge GNURadio 3.8.2 and UHD 3.15.0 loaded. USRP: USRP1 with a DBSRX.  Behavior is replicated with the EPEL8 UHD 3.15 packages, run as root. Question: what version of UHD do I need to downgrade to in order for 'ye olde DBSRX' daughterboard to be recognized and used?  I am not interested in upgrading the USRP at this time (unless someone knows of a newer unit that can be donated to our 501(c)(3) nonprofit; we'll take a donation of equipment, for sure!) since we have three USRP1's loaded with DBSRX daughterboards already that have worked in the past and are already characterized for our application.  Yes, I know the USRP1 is old, and the DBSRX is old, but they still work, they cost quite a bit of money under a federal grant (NSF), and they're characterized for our application here.  Plus, in this application I actually need the extra 100MHz from 2.3GHz to 2.4GHz that the original DBSRX can tune.  The USRPs have been stored for a few years; they were used for a couple of years about ten years ago and then shelved, but we want to start using them again (long story).  (It should go without saying that I'm not interested in running a ten year old OS or really old GNUradio; there are newer modules that I need to be able to use; just looking for last version of UHD that actually supported DBSRX).  Or if there is a workaround for UHD 3.15 to get a DBSRX to work. Here's the output of uhd_usrp_probe: (base) [pari-sdr@dhcp-pool167 ~]$ uhd_usrp_probe --args="type=usrp1" [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; UHD_3.15.0.HEAD-release [INFO] [FX2] Loading firmware image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx... [INFO] [FX2] Firmware loaded [INFO] [USRP1] Opening a USRP1 device... [INFO] [FX2] Loading FPGA image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf... [INFO] [FX2] FPGA image loaded [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... [ERROR] [DBMGR] The daughterboard manager encountered a recoverable error in init. Loading the "unknown" daughterboard implementations to continue. The daughterboard cannot operate until this error is resolved. AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6   in double dbsrx::set_lo_freq(double)   at /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306   _____________________________________________________  / |       Device: USRP1 Device |     _____________________________________________________ |    / |   |       Mboard: USRP1 |   |   serial: 4460cd30 |   | |   |   Time sources:  none |   |   Clock sources: internal |   |   Sensors: |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 0 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 1 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: A |   |   |   ID: DBSRX (0x0002) |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 0 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 1 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: A |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB (base) [pari-sdr@dhcp-pool167 ~]$ Thanks in advance!

On 11/16/2020 10:26 AM, Lamar Owen via USRP-users wrote: > System: CentOS 8 using Anaconda3 with the conda-forge GNURadio 3.8.2 > and UHD 3.15.0 loaded. > USRP: USRP1 with a DBSRX. Behavior is replicated with the EPEL8 UHD > 3.15 packages, run as root. > > Question: what version of UHD do I need to downgrade to in order for > 'ye olde DBSRX' daughterboard to be recognized and used? I am not > interested in upgrading the USRP at this time (unless someone knows of > a newer unit that can be donated to our 501(c)(3) nonprofit; we'll > take a donation of equipment, for sure!) since we have three USRP1's > loaded with DBSRX daughterboards already that have worked in the past > and are already characterized for our application. Yes, I know the > USRP1 is old, and the DBSRX is old, but they still work, they cost > quite a bit of money under a federal grant (NSF), and they're > characterized for our application here. Plus, in this application I > actually need the extra 100MHz from 2.3GHz to 2.4GHz that the original > DBSRX can tune. The USRPs have been stored for a few years; they were > used for a couple of years about ten years ago and then shelved, but > we want to start using them again (long story). (It should go without > saying that I'm not interested in running a ten year old OS or really > old GNUradio; there are newer modules that I need to be able to use; > just looking for last version of UHD that actually supported DBSRX). > Or if there is a workaround for UHD 3.15 to get a DBSRX to work. > > Here's the output of uhd_usrp_probe: > (base) [pari-sdr@dhcp-pool167 ~]$ uhd_usrp_probe --args="type=usrp1" > [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; > UHD_3.15.0.HEAD-release > [INFO] [FX2] Loading firmware image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx... > [INFO] [FX2] Firmware loaded > [INFO] [USRP1] Opening a USRP1 device... > [INFO] [FX2] Loading FPGA image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf... > [INFO] [FX2] FPGA image loaded > [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... > [ERROR] [DBMGR] The daughterboard manager encountered a recoverable > error in init. > Loading the "unknown" daughterboard implementations to continue. > The daughterboard cannot operate until this error is resolved. > AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 > in double dbsrx::set_lo_freq(double) > at > /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 > The general policy has always been that old hardware would be supported in newer versions of the software--although it may not get "new" features. The problem with running an older UHD is that it may not support newer Gnu Radio (3.8 and newer). My recollection is that the last time I tried USRP1 it worked, and that it was UHD 3.10. I'm not aware of any *conscious* decision not to support original USRP1+DBX in UHD versions going forward.

On 11/16/20 1:12 PM, Marcus D. Leech via USRP-users wrote: > On 11/16/2020 10:26 AM, Lamar Owen via USRP-users wrote: >> ... >> AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 >>   in double dbsrx::set_lo_freq(double) >>   at >> /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 >> > The general policy has always been that old hardware would be > supported in newer versions of the software--although it may not >   get "new" features. > > The problem with running an older UHD is that it may not support newer > Gnu Radio (3.8 and newer).  My recollection is that the last >   time I tried USRP1 it worked, and that it was UHD 3.10.   I'm not > aware of any *conscious* decision not to support original USRP1+DBX >   in UHD versions going forward. I wasn't able to find a statement to that effect either, and looking through the sources it looks like it should work.  Perhaps I need to specify a parameter to satisfy the AssertionError?  I don't recall seeing that back when I was using these three USRP1s on a frequent basis.  The same error does occur with both of the other USRP1s, it's not isolated to just the one.  I did find at least one other report of the same error, as well as your response, back in 2018. That one appeared to be cleared by checking to see if more than one copy of UHD in the path, and I don't find any.

On 11/16/20 2:20 PM, Lamar Owen via USRP-users wrote: > On 11/16/20 1:12 PM, Marcus D. Leech via USRP-users wrote: >> On 11/16/2020 10:26 AM, Lamar Owen via USRP-users wrote: >>> ... >>> AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 >>>   in double dbsrx::set_lo_freq(double) >>>   at >>> /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 >>> >> The general policy has always been that old hardware would be >> supported in newer versions of the software--although it may not >>   get "new" features. >> >> The problem with running an older UHD is that it may not support >> newer Gnu Radio (3.8 and newer).  My recollection is that the last >>   time I tried USRP1 it worked, and that it was UHD 3.10.   I'm not >> aware of any *conscious* decision not to support original USRP1+DBX >>   in UHD versions going forward. > I wasn't able to find a statement to that effect either, and looking > through the sources it looks like it should work.  Perhaps I need to > specify a parameter to satisfy the AssertionError?  I don't recall > seeing that back when I was using these three USRP1s on a frequent > basis.  The same error does occur with both of the other USRP1s, it's > not isolated to just the one.  I did find at least one other report of > the same error, as well as your response, back in 2018. That one > appeared to be cleared by checking to see if more than one copy of UHD > in the path, and I don't find any. So, I'm looking at issue report #304 related to the RFX board, and a related text patch file, https://github.com/EttusResearch/uhd/files/3881213/0001-rfx-Fix-calculation-of-prescaler-and-band-select.patch.txt that seem to have a similar construct in https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/dboard/db_dbsrx.cpp along about line 302.  Am I barking up the wrong tree, or if the 'for (auto ....' construct needed changing in one case it needs changing in this case, too?  I'll need to move from the conda package to the EPEL8 RPM package, because I know how to rebuild those and can test patches with those.  I don't know enough c++ to be able to generate the patch, though.

On 11/16/20 3:14 PM, Lamar Owen via USRP-users wrote: > So, I'm looking at issue report #304 related to the RFX board, and a > related text patch file, > https://github.com/EttusResearch/uhd/files/3881213/0001-rfx-Fix-calculation-of-prescaler-and-band-select.patch.txt > that seem to have a similar construct in > https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/dboard/db_dbsrx.cpp > along about line 302.  Am I barking up the wrong tree, or if the 'for > (auto ....' construct needed changing in one case it needs changing in > this case, too?  I'll need to move from the conda package to the EPEL8 > RPM package, because I know how to rebuild those and can test patches > with those.  I don't know enough c++ to be able to generate the patch, > though. Just in case this helps, here's logging output: (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; UHD_3.15.0.HEAD-release [DEBUG] [MPMD] Discovering MPM devices on port 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 [DEBUG] [USRP1] USRP1 firmware image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 [TRACE] [UHD] Device hash: 6433317707856818692 [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf [INFO] [USRP1] Opening a USRP1 device... [DEBUG] [USRP1] USRP1 FPGA image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf [TRACE] [USRP1] poke32(13, 0x       0) [TRACE] [USRP1] poke32(14, 0x       0) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [DEBUG] [USRP1] USRP1 Capabilities    number of duc's: 2    number of ddc's: 2    rx halfband:     1    tx halfband:     0 [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32(16, 0x       0) [TRACE] [USRP1] poke32(17, 0x       0) [TRACE] [USRP1] poke32(15, 0x       3) [TRACE] [USRP1] poke32(18, 0x       0) [TRACE] [USRP1] poke32(19, 0x       0) [TRACE] [USRP1] poke32(15, 0x       f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V [TRACE] [USRP1] codec control write reg: 0x    24d1 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9425  num_bits: 16 readback: 0 [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0005, num_bytes 1 [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 6, 0xffff0001) [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 [TRACE] [DBSRX] DBSRX R:2 [ERROR] [DBMGR] The daughterboard manager encountered a recoverable error in init. Loading the "unknown" daughterboard implementations to continue. The daughterboard cannot operate until this error is resolved. AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6   in double dbsrx::set_lo_freq(double)   at /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 1, 0x       1) [TRACE] [USRP1] poke32(33, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 0, 0x       1) [TRACE] [USRP1] poke32(32, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32(34, 0x       0) [TRACE] [USRP1] poke32(35, 0x       0) [TRACE] [USRP1] poke32(38, 0x      41) [TRACE] [USRP1] poke32(39, 0x     981)   _____________________________________________________  / |       Device: USRP1 Device |     _____________________________________________________ |    / |   |       Mboard: USRP1 |   |   serial: 4460cd30 |   | |   |   Time sources:  none |   |   Clock sources: internal |   |   Sensors: |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 0 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 1 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: A |   |   |   ID: DBSRX (0x0002) |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 0 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 1 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: A |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2063  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2063  num_bits: 16 readback: 0 (base) [pari-sdr@dhcp-pool167 ~]$ And with a second USRP1: (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; UHD_3.15.0.HEAD-release [DEBUG] [MPMD] Discovering MPM devices on port 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 [DEBUG] [USRP1] USRP1 firmware image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx [INFO] [FX2] Loading firmware image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx... [INFO] [FX2] Firmware loaded [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 [TRACE] [UHD] Device hash: 11462434024067858173 [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf [INFO] [USRP1] Opening a USRP1 device... [DEBUG] [USRP1] USRP1 FPGA image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf [INFO] [FX2] Loading FPGA image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf... [INFO] [FX2] FPGA image loaded [TRACE] [USRP1] poke32(13, 0x       0) [TRACE] [USRP1] poke32(14, 0x       0) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [DEBUG] [USRP1] USRP1 Capabilities    number of duc's: 2    number of ddc's: 2    rx halfband:     1    tx halfband:     0 [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32(16, 0x       0) [TRACE] [USRP1] poke32(17, 0x       0) [TRACE] [USRP1] poke32(15, 0x       3) [TRACE] [USRP1] poke32(18, 0x       0) [TRACE] [USRP1] poke32(19, 0x       0) [TRACE] [USRP1] poke32(15, 0x       f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V [TRACE] [USRP1] codec control write reg: 0x    24d1 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9425  num_bits: 16 readback: 0 [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0005, num_bytes 1 [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 6, 0xffff0001) [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 [TRACE] [DBSRX] DBSRX R:2 [ERROR] [DBMGR] The daughterboard manager encountered a recoverable error in init. Loading the "unknown" daughterboard implementations to continue. The daughterboard cannot operate until this error is resolved. AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6   in double dbsrx::set_lo_freq(double)   at /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 1, 0x       1) [TRACE] [USRP1] poke32(33, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 0, 0x       1) [TRACE] [USRP1] poke32(32, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32(34, 0x       0) [TRACE] [USRP1] poke32(35, 0x       0) [TRACE] [USRP1] poke32(38, 0x      41) [TRACE] [USRP1] poke32(39, 0x     981)   _____________________________________________________  / |       Device: USRP1 Device |     _____________________________________________________ |    / |   |       Mboard: USRP1 |   |   serial: 45d0d3fa |   | |   |   Time sources:  none |   |   Clock sources: internal |   |   Sensors: |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 0 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 1 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: A |   |   |   ID: DBSRX (0x0002) |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 0 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 1 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: A |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2063  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2063  num_bits: 16 readback: 0 (base) [pari-sdr@dhcp-pool167 ~]$

On 11/16/2020 03:32 PM, Lamar Owen via USRP-users wrote: > On 11/16/20 3:14 PM, Lamar Owen via USRP-users wrote: >> So, I'm looking at issue report #304 related to the RFX board, and a >> related text patch file, >> https://github.com/EttusResearch/uhd/files/3881213/0001-rfx-Fix-calculation-of-prescaler-and-band-select.patch.txt >> that seem to have a similar construct in >> https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/dboard/db_dbsrx.cpp >> along about line 302. Am I barking up the wrong tree, or if the 'for >> (auto ....' construct needed changing in one case it needs changing >> in this case, too? I'll need to move from the conda package to the >> EPEL8 RPM package, because I know how to rebuild those and can test >> patches with those. I don't know enough c++ to be able to generate >> the patch, though. > Just in case this helps, here's logging output: > (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe > [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; > UHD_3.15.0.HEAD-release > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 > [DEBUG] [USRP1] USRP1 firmware image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 > [TRACE] [UHD] Device hash: 6433317707856818692 > [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf > [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf > [INFO] [USRP1] Opening a USRP1 device... > [DEBUG] [USRP1] USRP1 FPGA image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf > [TRACE] [USRP1] poke32(13, 0x 0) > [TRACE] [USRP1] poke32(14, 0x 0) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [DEBUG] [USRP1] USRP1 Capabilities number of duc's: 2 number of > ddc's: 2 rx halfband: 1 tx halfband: 0 > [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32(16, 0x 0) > [TRACE] [USRP1] poke32(17, 0x 0) > [TRACE] [USRP1] poke32(15, 0x 3) > [TRACE] [USRP1] poke32(18, 0x 0) > [TRACE] [USRP1] poke32(19, 0x 0) > [TRACE] [USRP1] poke32(15, 0x f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V > [TRACE] [USRP1] codec control write reg: 0x 24d1 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9425 num_bits: 16 > readback: 0 > [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0005, num_bytes 1 > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 6, 0xffff0001) > [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 > [TRACE] [DBSRX] DBSRX R:2 > > [ERROR] [DBMGR] The daughterboard manager encountered a recoverable > error in init. > Loading the "unknown" daughterboard implementations to continue. > The daughterboard cannot operate until this error is resolved. > AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 > in double dbsrx::set_lo_freq(double) > at > /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 > > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 1, 0x 1) > [TRACE] [USRP1] poke32(33, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 0, 0x 1) > [TRACE] [USRP1] poke32(32, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32(34, 0x 0) > [TRACE] [USRP1] poke32(35, 0x 0) > [TRACE] [USRP1] poke32(38, 0x 41) > [TRACE] [USRP1] poke32(39, 0x 981) > _____________________________________________________ > / > | Device: USRP1 Device > | _____________________________________________________ > | / > | | Mboard: USRP1 > | | serial: 4460cd30 > | | > | | Time sources: none > | | Clock sources: internal > | | Sensors: > | | _____________________________________________________ > | | / > | | | RX DSP: 0 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX DSP: 1 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX Dboard: A > | | | ID: DBSRX (0x0002) > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | RX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | TX DSP: 0 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX DSP: 1 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX Dboard: A > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > | | _____________________________________________________ > | | / > | | | TX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2063 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2063 num_bits: 16 > readback: 0 > (base) [pari-sdr@dhcp-pool167 ~]$ > > And with a second USRP1: > (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe > [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; > UHD_3.15.0.HEAD-release > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 > [DEBUG] [USRP1] USRP1 firmware image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx > [INFO] [FX2] Loading firmware image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx... > [INFO] [FX2] Firmware loaded > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 > [TRACE] [UHD] Device hash: 11462434024067858173 > [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf > [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf > [INFO] [USRP1] Opening a USRP1 device... > [DEBUG] [USRP1] USRP1 FPGA image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf > [INFO] [FX2] Loading FPGA image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf... > [INFO] [FX2] FPGA image loaded > [TRACE] [USRP1] poke32(13, 0x 0) > [TRACE] [USRP1] poke32(14, 0x 0) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [DEBUG] [USRP1] USRP1 Capabilities number of duc's: 2 number of > ddc's: 2 rx halfband: 1 tx halfband: 0 > [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32(16, 0x 0) > [TRACE] [USRP1] poke32(17, 0x 0) > [TRACE] [USRP1] poke32(15, 0x 3) > [TRACE] [USRP1] poke32(18, 0x 0) > [TRACE] [USRP1] poke32(19, 0x 0) > [TRACE] [USRP1] poke32(15, 0x f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V > [TRACE] [USRP1] codec control write reg: 0x 24d1 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9425 num_bits: 16 > readback: 0 > [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0005, num_bytes 1 > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 6, 0xffff0001) > [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 > [TRACE] [DBSRX] DBSRX R:2 > > [ERROR] [DBMGR] The daughterboard manager encountered a recoverable > error in init. > Loading the "unknown" daughterboard implementations to continue. > The daughterboard cannot operate until this error is resolved. > AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 > in double dbsrx::set_lo_freq(double) > at > /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 > > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 1, 0x 1) > [TRACE] [USRP1] poke32(33, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 0, 0x 1) > [TRACE] [USRP1] poke32(32, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32(34, 0x 0) > [TRACE] [USRP1] poke32(35, 0x 0) > [TRACE] [USRP1] poke32(38, 0x 41) > [TRACE] [USRP1] poke32(39, 0x 981) > _____________________________________________________ > / > | Device: USRP1 Device > | _____________________________________________________ > | / > | | Mboard: USRP1 > | | serial: 45d0d3fa > | | > | | Time sources: none > | | Clock sources: internal > | | Sensors: > | | _____________________________________________________ > | | / > | | | RX DSP: 0 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX DSP: 1 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX Dboard: A > | | | ID: DBSRX (0x0002) > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | RX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | TX DSP: 0 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX DSP: 1 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX Dboard: A > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > | | _____________________________________________________ > | | / > | | | TX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2063 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2063 num_bits: 16 > readback: 0 > (base) [pari-sdr@dhcp-pool167 ~]$ > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com I'll note that there was a fair amount of churn between UHD 3.15 and UHD 4.0 on dbs_rx -- whether that fixes this issue or not is another matter.

On 11/16/2020 03:32 PM, Lamar Owen via USRP-users wrote: > > > [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 > [TRACE] [DBSRX] DBSRX R:2 > > [ERROR] [DBMGR] The daughterboard manager encountered a recoverable > error in init. > Loading the "unknown" daughterboard implementations to continue. > The daughterboard cannot operate until this error is resolved. > AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 > in double dbsrx::set_lo_freq(double) > at > /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 If you look at the context of this assertion--it should never be asserted. ref_clock is 4e6 and m is 4, so the test is satisfied, and therefore the assertion shouldn't fail. I wonder if this is a compiler issue, or an issue with the UHD_ASSERT logic? > > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 1, 0x 1) > [TRACE] [USRP1] poke32(33, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 0, 0x 1) > [TRACE] [USRP1] poke32(32, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32(34, 0x 0) > [TRACE] [USRP1] poke32(35, 0x 0) > [TRACE] [USRP1] poke32(38, 0x 41) > [TRACE] [USRP1] poke32(39, 0x 981) > _____________________________________________________ > / > | Device: USRP1 Device > | _____________________________________________________ > | / > | | Mboard: USRP1 > | | serial: 45d0d3fa > | | > | | Time sources: none > | | Clock sources: internal > | | Sensors: > | | _____________________________________________________ > | | / > | | | RX DSP: 0 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX DSP: 1 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX Dboard: A > | | | ID: DBSRX (0x0002) > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | RX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | TX DSP: 0 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX DSP: 1 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX Dboard: A > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > | | _____________________________________________________ > | | / > | | | TX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > https://www.amazon.ca/Breakout-Connector-Female-Adapter-Terminal/dp/B07DL13B32/ref=sr_1_23_sspa?dchild=1&gclid=Cj0KCQiA48j9BRC-ARIsAMQu3WS6mqz1QoEYjrHj2vHgONo0eOz7jWLd7vf1879y7aTpPzTauZuEmF8aAvu5EALw_wcB&hvadid=208320688227&hvdev=c&hvlocphy=9000707&hvnetw=g&hvqmt=e&hvrand=9845139346444461649&hvtargid=kwd-301399804745&hydadcr=1500_9454465&keywords=usb+to+rs-232&qid=1605565159&sr=8-23-spons&tag=googcana-20&psc=1&spLa=ZW5jcnlwdGVkUXVhbGlmaWVyPUE3N1BFTEhCQjBFVzImZW5jcnlwdGVkSWQ9QTAxODU5NjgyU0NJT0EwRUFXTllZJmVuY3J5cHRlZEFkSWQ9QTAzMTcwMTUxSDdXTFpLRERMR1BJJndpZGdldE5hbWU9c3BfbXRmJmFjdGlvbj1jbGlja1JlZGlyZWN0JmRvTm90TG9nQ2xpY2s9dHJ1ZQ== > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2063 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2063 num_bits: 16 > readback: 0 > (base) [pari-sdr@dhcp-pool167 ~]$ > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

On 11/16/20 5:26 PM, Marcus D. Leech via USRP-users wrote: > On 11/16/2020 03:32 PM, Lamar Owen via USRP-users wrote: >> >> >> [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 >> [TRACE] [DBSRX] DBSRX R:2 >> >> [ERROR] [DBMGR] The daughterboard manager encountered a recoverable >> error in init. >> Loading the "unknown" daughterboard implementations to continue. >> The daughterboard cannot operate until this error is resolved. >> AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 >>   in double dbsrx::set_lo_freq(double) >>   at >> /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 > If you look at the context of this assertion--it should never be > asserted.   ref_clock is 4e6 and m is 4, so the test is satisfied, and > therefore the >   assertion shouldn't fail.  I wonder if this is a compiler issue, or > an issue with the UHD_ASSERT logic? Yeah, I saw that; thanks for the pointer (to someone else's question) about logging at trace level.  So I've filed it as an issue in the UHD github.  Could be something similar to issue #304 at the UHD github. What it does tell me is that 3.15 SHOULD support USRP1 with DBSRX, just need to fix the issue.

On 11/16/2020 05:38 PM, Lamar Owen wrote: > On 11/16/20 5:26 PM, Marcus D. Leech via USRP-users wrote: >> On 11/16/2020 03:32 PM, Lamar Owen via USRP-users wrote: >>> >>> >>> [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 >>> [TRACE] [DBSRX] DBSRX R:2 >>> >>> [ERROR] [DBMGR] The daughterboard manager encountered a recoverable >>> error in init. >>> Loading the "unknown" daughterboard implementations to continue. >>> The daughterboard cannot operate until this error is resolved. >>> AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 >>> in double dbsrx::set_lo_freq(double) >>> at >>> /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 >> If you look at the context of this assertion--it should never be >> asserted. ref_clock is 4e6 and m is 4, so the test is satisfied, >> and therefore the >> assertion shouldn't fail. I wonder if this is a compiler issue, or >> an issue with the UHD_ASSERT logic? > > Yeah, I saw that; thanks for the pointer (to someone else's question) > about logging at trace level. So I've filed it as an issue in the UHD > github. Could be something similar to issue #304 at the UHD github. > > What it does tell me is that 3.15 SHOULD support USRP1 with DBSRX, > just need to fix the issue. I can confirm that this issue goes back at least as far as UHD 3.13 -- just tried it after digging my USRP1 and DBSRX cards out of storage.