hi, in X310 FPGA code ，I have some problems about timing ,and hope you can help me. e.g ,in noc_block_fft.v, clk_in（that is radio_clk:200M） ------>DCM ip core(pll)----> clkout ：114.688M, implement ,and some problems about timing . then I set false-path from ... to ... ,but timing still wrong.Can you help me？ Importantly，in X310 FPGA code ，all the modules' the main clock is 200MHz, butmy block need is 114.688MHz, which can be achieved? At 2017-05-03 09:35:35, "Jonathon Pendlum" <jonathon.pendlum@ettus.com> wrote: I would suggest making two counters. One that continuously increments (lets call it 'count') and another that only increments when m_axis_data_tvalid & m_axis_data_tready are both asserted (lets call it 'valid_count'). Make the counters 'count' and 'valid_count' 48 bits wide. Then use chipscope to see the value of those counters after running your flowgraph for a few minutes. Throughput = valid_count / count. I would also suggest having your custom block just loopback AXI Wrapper's output to its input (m_axis_data_tdata -> s_axis_data_tdata) so your block's logic does not interfere with this throughput calculation. On Tue, May 2, 2017 at 8:07 PM, Lihua Ren <anything292@163.com> wrote: hi,Jonathon My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC ---> RFnoc:my block, in radio block, sampling rate :200MHz, in DDC block ，input rate :200MHz,output rate :200kHz, then, in my block ,I think the data rate in the FPGA code should be :200kHz ，but the use of ChipScope to see the data rate is about 1.67MHz. 1.67MHz = The number of sampling data *(1/200MHz) ,200 Mhz is ila core 's clk. Since RFNoC is packetized, you will see bursts of data。You're right ！but I can calculate i_valid cycle in my block 。I need continuous data, using the RAM IP core cache to ensure subsequent work 。Is that true？ At 2017-05-02 22:55:18, "Jonathon Pendlum" <jonathon.pendlum@ettus.com> wrote: Hi, How are you measuring the sample rate in your block? Since RFNoC is packetized, you will see bursts of data, so you need to find the average rate over many clock cycles. What does the console log say? Do you see any warnings about the sample rate? Jonathon On May 2, 2017 7:55 AM, "Lihua Ren via USRP-users" <usrp-users@lists.ettus.com> wrote: hi, My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC ---> RFnoc:my block, in radio block, sampling rate :200MHz, in DDC block ，input rate :200MHz,output rate :200kHz, I think the data rate in the FPGA code should be :200kHz ，but the use of ChipScope to see the data rate is about 1.67MHz.why? Thanks. _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hi, Why do you need a clock rate of 114.688 MHz for your block? Jonathon On Sun, May 14, 2017 at 7:30 PM, Lihua Ren via USRP-users < usrp-users@lists.ettus.com> wrote: > hi, > > > in X310 FPGA code ，I have some problems about timing ,and hope you can > help me. e.g ,in noc_block_fft.v, clk_in（that is radio_clk:200M） > ------>DCM ip core(pll)----> clkout ：114.688M, implement ,and some > problems about timing . then I set false-path from ... to ... ,but timing still > wrong.Can you help me？ > > Importantly，in X310 FPGA code ，all the modules' the main clock is 200MHz, > butmy block need is 114.688MHz, which can be achieved? > > At 2017-05-03 09:35:35, "Jonathon Pendlum" <jonathon.pendlum@ettus.com> > wrote: > > I would suggest making two counters. One that continuously increments > (lets call it 'count') and another that only increments when > m_axis_data_tvalid & m_axis_data_tready are both asserted (lets call it > 'valid_count'). Make the counters 'count' and 'valid_count' 48 bits wide. > Then use chipscope to see the value of those counters after running your > flowgraph for a few minutes. Throughput = valid_count / count. > > I would also suggest having your custom block just loopback AXI Wrapper's > output to its input (m_axis_data_tdata -> s_axis_data_tdata) so your > block's logic does not interfere with this throughput calculation. > > On Tue, May 2, 2017 at 8:07 PM, Lihua Ren <anything292@163.com> wrote: > >> >> hi,Jonathon >> >> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC ---> >> RFnoc:my block, >> in radio block, sampling rate :200MHz, >> in DDC block ，input rate :200MHz,output rate :200kHz, >> then, in my block ,I think the data rate in the FPGA code should be :200kHz ，but >> the use of ChipScope to see the data rate is about 1.67MHz. >> >> 1.67MHz = The number of sampling data *(1/200MHz) ,200 Mhz is ila core >> 's clk. >> >> Since RFNoC is packetized, you will see bursts of data。You're right ！but >> I can calculate i_valid cycle in my block 。I need continuous data, using >> the RAM IP core cache to ensure subsequent work 。Is that true？ >> >> At 2017-05-02 22:55:18, "Jonathon Pendlum" <jonathon.pendlum@ettus.com> >> wrote: >> >> Hi, >> >> How are you measuring the sample rate in your block? Since RFNoC is >> packetized, you will see bursts of data, so you need to find the average >> rate over many clock cycles. >> >> What does the console log say? Do you see any warnings about the sample >> rate? >> >> >> >> Jonathon >> >> On May 2, 2017 7:55 AM, "Lihua Ren via USRP-users" < >> usrp-users@lists.ettus.com> wrote: >> >>> hi, >>> My design is as follows :in GNUradio, RFnoc: radio-->RFnoc: DDC ---> >>> RFnoc:my block, >>> in radio block, sampling rate :200MHz, >>> in DDC block ，input rate :200MHz,output rate :200kHz, >>> I think the data rate in the FPGA code should be :200kHz ，but the use >>> of ChipScope to see the data rate is about 1.67MHz.why? >>> Thanks. >>> >>> >>> >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> >> >> > > > > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >