Hello , I want to synthesize the project .xise generated by the makefile provided by GitHub ( USRP3 / top / b200 ) to generate a new FPGA bitstream with some more verilog modules created by me , but when I open the project with ISE14.7 i can't synthesize because of errors. How should I proceed to generate the project to make changes?ThanksEzequiel

Ezequiel, You should use the Makefile to directly synthesize new B200 images, this is the only supported build methodology. Review usrp3/top/b200/Makefile.b200.inc and also usrp3/lib/*/Makefile.srcs to see how to add new source files to the project. -Ian On Jul 3, 2015, at 9:47 AM, Ezequiel via USRP-users <usrp-users@lists.ettus.com> wrote: > Hello , I want to synthesize the project .xise generated by the makefile provided by GitHub ( USRP3 / top / b200 ) to generate a new FPGA bitstream with some more verilog modules created by me , but when I open the project with ISE14.7 i can't synthesize because of errors. How should I proceed to generate the project to make changes? > Thanks > Ezequiel > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com