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Discussion and technical support related to USRP, UHD, RFNoC
View all threadsTuning Resolution of B210 RF Front end
Using the functions multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed to get the low, high, and
step size of just the RF front end (without the DSP chain). However, when
I looked at the attributes of both freq_range_t objects that were returned,
the start is 50MHz, the stop is 6GHz, but the step size was set to 0.
What is the step size of the RF Front End on the B210 (without the DSP)?
Thanks,
-Jeremy
On 05/26/2016 06:17 PM, Jeremy Hershberger via USRP-users wrote:
Using the functions multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed to get the low, high,
and step size of just the RF front end (without the DSP chain).
However, when I looked at the attributes of both freq_range_t objects
that were returned, the start is 50MHz, the stop is 6GHz, but the step
size was set to 0.
What is the step size of the RF Front End on the B210 (without the DSP)?
Thanks,
-Jeremy
It depends on the master-clock setting, almost certainly, and the B2xx
have variable master-clock rates. Ettus engineers can comment
further on why this value is set to zero, but my guess it's due to
the above....
2.4Hz for AD9361
-Ian
On Thu, May 26, 2016 at 3:26 PM, Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
On 05/26/2016 06:17 PM, Jeremy Hershberger via USRP-users wrote:
Using the functions multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed to get the low, high, and
step size of just the RF front end (without the DSP chain). However, when
I looked at the attributes of both freq_range_t objects that were returned,
the start is 50MHz, the stop is 6GHz, but the step size was set to 0.
What is the step size of the RF Front End on the B210 (without the DSP)?
Thanks,
-Jeremy
It depends on the master-clock setting, almost certainly, and the B2xx
have variable master-clock rates. Ettus engineers can comment
further on why this value is set to zero, but my guess it's due to the
above....
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Ian,
I was able to tune to 50MHz and computed the difference between target and
actual frequency and got 0 Hz. (by examining the tune_result_t from the
set_rx_freq() and set_tx_freq() methods)
If I repeat the same test with a target freq of 50MHz+2.4Hz, I get a
difference of 0.0158099 Hz.
If the tuning resolution is in 2.4Hz steps, shouldn't I get a 0Hz
difference?
-Jeremy
On Thu, May 26, 2016 at 8:34 PM, Ian Buckley via USRP-users <
usrp-users@lists.ettus.com> wrote:
2.4Hz for AD9361
-Ian
On Thu, May 26, 2016 at 3:26 PM, Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
On 05/26/2016 06:17 PM, Jeremy Hershberger via USRP-users wrote:
Using the functions multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed to get the low, high, and
step size of just the RF front end (without the DSP chain). However, when
I looked at the attributes of both freq_range_t objects that were returned,
the start is 50MHz, the stop is 6GHz, but the step size was set to 0.
What is the step size of the RF Front End on the B210 (without the DSP)?
Thanks,
-Jeremy
It depends on the master-clock setting, almost certainly, and the B2xx
have variable master-clock rates. Ettus engineers can comment
further on why this value is set to zero, but my guess it's due to the
above....
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
On 05/27/2016 04:02 PM, Jeremy Hershberger wrote:
Ian,
I was able to tune to 50MHz and computed the difference between target
and actual frequency and got 0 Hz. (by examining the tune_result_t
from the set_rx_freq() and set_tx_freq() methods)
If I repeat the same test with a target freq of 50MHz+2.4Hz, I get a
difference of 0.0158099 Hz.
If the tuning resolution is in 2.4Hz steps, shouldn't I get a 0Hz
difference?
-Jeremy
Probably just some floating-point rounding going on somewhere in the stack.
But to put this in perspective, a difference of 0.0158099 Hz is 0.3PPB
at your desired center frequency. Since you likely aren't using a
reference that is that good, a disagreement in what the Fc is of
0.3PPB makes utterly no difference.
Further, since we're talking about floating-point here, it is unsound
programming practice to do something like:
if (value_that_was_computed == value_that_is_a_constant)
When using finite-precision floating-point math. So if this
0.01558Hz difference is important because you're doing comparisons like the
above, consider using a "isnearlythesameas()" type operation.
On Thu, May 26, 2016 at 8:34 PM, Ian Buckley via USRP-users
<usrp-users@lists.ettus.com mailto:usrp-users@lists.ettus.com> wrote:
2.4Hz for AD9361
-Ian
On Thu, May 26, 2016 at 3:26 PM, Marcus D. Leech via USRP-users
<usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>>
wrote:
On 05/26/2016 06:17 PM, Jeremy Hershberger via USRP-users wrote:
Using the functions multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed to get
the low, high, and step size of just the RF front end
(without the DSP chain). However, when I looked at the
attributes of both freq_range_t objects that were
returned, the start is 50MHz, the stop is 6GHz, but the
step size was set to 0.
What is the step size of the RF Front End on the B210
(without the DSP)?
Thanks,
-Jeremy
It depends on the master-clock setting, almost certainly, and
the B2xx have variable master-clock rates. Ettus engineers
can comment
further on why this value is set to zero, but my guess it's
due to the above....
_______________________________________________
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USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
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USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>
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Jeremy FWIW That number is straight from ADI's data book, I haven't tried
to derive it by reverse engineering the synthesizer design. It may for
example be a worst case example at the upper frequency limit rather than a
fixed granularity over the whole frequency range. What happens if you go
repeat your experiment up near 6GHz?
-Ian
On Fri, May 27, 2016 at 1:10 PM, Marcus D. Leech mleech@ripnet.com wrote:
On 05/27/2016 04:02 PM, Jeremy Hershberger wrote:
Ian,
I was able to tune to 50MHz and computed the difference between target and
actual frequency and got 0 Hz. (by examining the tune_result_t from the
set_rx_freq() and set_tx_freq() methods)
If I repeat the same test with a target freq of 50MHz+2.4Hz, I get a
difference of 0.0158099 Hz.
If the tuning resolution is in 2.4Hz steps, shouldn't I get a 0Hz
difference?
-Jeremy
Probably just some floating-point rounding going on somewhere in the stack.
But to put this in perspective, a difference of 0.0158099 Hz is 0.3PPB at
your desired center frequency. Since you likely aren't using a
reference that is that good, a disagreement in what the Fc is of 0.3PPB
makes utterly no difference.
Further, since we're talking about floating-point here, it is unsound
programming practice to do something like:
if (value_that_was_computed == value_that_is_a_constant)
When using finite-precision floating-point math. So if this 0.01558Hz
difference is important because you're doing comparisons like the
above, consider using a "isnearlythesameas()" type operation.
On Thu, May 26, 2016 at 8:34 PM, Ian Buckley via USRP-users <
usrp-users@lists.ettus.com> wrote:
2.4Hz for AD9361
-Ian
On Thu, May 26, 2016 at 3:26 PM, Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
On 05/26/2016 06:17 PM, Jeremy Hershberger via USRP-users wrote:
Using the functions multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed to get the low, high, and
step size of just the RF front end (without the DSP chain). However, when
I looked at the attributes of both freq_range_t objects that were returned,
the start is 50MHz, the stop is 6GHz, but the step size was set to 0.
What is the step size of the RF Front End on the B210 (without the DSP)?
Thanks,
-Jeremy
It depends on the master-clock setting, almost certainly, and the B2xx
have variable master-clock rates. Ettus engineers can comment
further on why this value is set to zero, but my guess it's due to the
above....
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Ian,
I repeated the experiment @ 5.9GHz, which is an even 2.4Hz divisor and got
2.38419Hz.
I was thinking that the actual tuning frequency was just a LUT value from
the LO frac PLL divisor setting. But apparently, the value is being
measured somehow from the hardware.
On Fri, May 27, 2016 at 4:26 PM, Ian Buckley ianb@ionconcepts.com wrote:
Jeremy FWIW That number is straight from ADI's data book, I haven't tried
to derive it by reverse engineering the synthesizer design. It may for
example be a worst case example at the upper frequency limit rather than a
fixed granularity over the whole frequency range. What happens if you go
repeat your experiment up near 6GHz?
-Ian
On Fri, May 27, 2016 at 1:10 PM, Marcus D. Leech mleech@ripnet.com
wrote:
On 05/27/2016 04:02 PM, Jeremy Hershberger wrote:
Ian,
I was able to tune to 50MHz and computed the difference between target
and actual frequency and got 0 Hz. (by examining the tune_result_t from the
set_rx_freq() and set_tx_freq() methods)
If I repeat the same test with a target freq of 50MHz+2.4Hz, I get a
difference of 0.0158099 Hz.
If the tuning resolution is in 2.4Hz steps, shouldn't I get a 0Hz
difference?
-Jeremy
Probably just some floating-point rounding going on somewhere in the
stack.
But to put this in perspective, a difference of 0.0158099 Hz is 0.3PPB at
your desired center frequency. Since you likely aren't using a
reference that is that good, a disagreement in what the Fc is of 0.3PPB
makes utterly no difference.
Further, since we're talking about floating-point here, it is unsound
programming practice to do something like:
if (value_that_was_computed == value_that_is_a_constant)
When using finite-precision floating-point math. So if this 0.01558Hz
difference is important because you're doing comparisons like the
above, consider using a "isnearlythesameas()" type operation.
On Thu, May 26, 2016 at 8:34 PM, Ian Buckley via USRP-users <
usrp-users@lists.ettus.com> wrote:
2.4Hz for AD9361
-Ian
On Thu, May 26, 2016 at 3:26 PM, Marcus D. Leech via USRP-users <
usrp-users@lists.ettus.com> wrote:
On 05/26/2016 06:17 PM, Jeremy Hershberger via USRP-users wrote:
Using the functions multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed to get the low, high, and
step size of just the RF front end (without the DSP chain). However, when
I looked at the attributes of both freq_range_t objects that were returned,
the start is 50MHz, the stop is 6GHz, but the step size was set to 0.
What is the step size of the RF Front End on the B210 (without the
DSP)?
Thanks,
-Jeremy
It depends on the master-clock setting, almost certainly, and the B2xx
have variable master-clock rates. Ettus engineers can comment
further on why this value is set to zero, but my guess it's due to
the above....
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
On 05/27/2016 04:51 PM, Jeremy Hershberger wrote:
Ian,
I repeated the experiment @ 5.9GHz, which is an even 2.4Hz divisor and
got 2.38419Hz.
I was thinking that the actual tuning frequency was just a LUT value
from the LO frac PLL divisor setting. But apparently, the value is
being measured somehow from the hardware.
It's not being measured, just calculated from the hardware parameters
(refclock frequency, PLL register widths, etc).
On Fri, May 27, 2016 at 4:26 PM, Ian Buckley <ianb@ionconcepts.com
mailto:ianb@ionconcepts.com> wrote:
Jeremy FWIW That number is straight from ADI's data book, I
haven't tried to derive it by reverse engineering the synthesizer
design. It may for example be a worst case example at the upper
frequency limit rather than a fixed granularity over the whole
frequency range. What happens if you go repeat your experiment up
near 6GHz?
-Ian
On Fri, May 27, 2016 at 1:10 PM, Marcus D. Leech
<mleech@ripnet.com <mailto:mleech@ripnet.com>> wrote:
On 05/27/2016 04:02 PM, Jeremy Hershberger wrote:
Ian,
I was able to tune to 50MHz and computed the difference
between target and actual frequency and got 0 Hz. (by
examining the tune_result_t from the set_rx_freq() and
set_tx_freq() methods)
If I repeat the same test with a target freq of 50MHz+2.4Hz,
I get a difference of 0.0158099 Hz.
If the tuning resolution is in 2.4Hz steps, shouldn't I get a
0Hz difference?
-Jeremy
Probably just some floating-point rounding going on somewhere
in the stack.
But to put this in perspective, a difference of 0.0158099 Hz
is 0.3PPB at your desired center frequency. Since you likely
aren't using a
reference that is that good, a disagreement in what the Fc
is of 0.3PPB makes utterly no difference.
Further, since we're talking about floating-point here, it is
unsound programming practice to do something like:
if (value_that_was_computed == value_that_is_a_constant)
When using finite-precision floating-point math. So if
this 0.01558Hz difference is important because you're doing
comparisons like the
above, consider using a "isnearlythesameas()" type operation.
On Thu, May 26, 2016 at 8:34 PM, Ian Buckley via USRP-users
<usrp-users@lists.ettus.com
<mailto:usrp-users@lists.ettus.com>> wrote:
2.4Hz for AD9361
-Ian
On Thu, May 26, 2016 at 3:26 PM, Marcus D. Leech via
USRP-users <usrp-users@lists.ettus.com
<mailto:usrp-users@lists.ettus.com>> wrote:
On 05/26/2016 06:17 PM, Jeremy Hershberger via
USRP-users wrote:
Using the functions
multi_usrp::get_fe_rx_freq_range() and
multi_usrp::get_fe_tx_freq_range() I am supposed
to get the low, high, and step size of just the
RF front end (without the DSP chain). However,
when I looked at the attributes of both
freq_range_t objects that were returned, the
start is 50MHz, the stop is 6GHz, but the step
size was set to 0.
What is the step size of the RF Front End on the
B210 (without the DSP)?
Thanks,
-Jeremy
It depends on the master-clock setting, almost
certainly, and the B2xx have variable master-clock
rates. Ettus engineers can comment
further on why this value is set to zero, but my
guess it's due to the above....
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
<mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
_______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
<mailto:USRP-users@lists.ettus.com>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com