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Leveraging Dual 10 Gigabit Ethernet SFP+ Ports

G
gechb21@gmail.com
Wed, Jul 16, 2025 1:53 PM

The USRP X310 uses dual 10 Gigabit Ethernet SFP+ ports to support high-throughput data transfers between the host and FPGA. I plan to transmit and receive samples in parallel over these two SFP+ ports using a single RF transmit and receive chain. The UHD driver on the host splits large transmission data streams across the two Ethernet links, sending them to the FPGA for processing. On the receive side, it similarly merges data streams coming back from the FPGA to form a continuous IQ sample stream for the host. Inside the FPGA, the split streams received over the two SFP+ ports are merged and assembled into complete IQ samples before being passed to the DAC for transmission. Conversely, on reception, the FPGA splits the ADC output streams and distributes them across the two SFP+ ports to maximize throughput back to the host server.

How exactly does the FPGA automatically merge the parallel Ethernet streams from SFP+0 and SFP+1 into one logical contiguous IQ stream before sending it to the DAC? And during reception, how does it coordinate splitting the ADC output to distribute data streams efficiently across both SFP+ ports? Is this merging and splitting entirely handled by the UHD and FPGA firmware, or do we need to implement custom Python/MATLAB/C++ code to manage it?

The USRP X310 uses dual 10 Gigabit Ethernet SFP+ ports to support high-throughput data transfers between the host and FPGA. I plan to transmit and receive samples in parallel over these two SFP+ ports using a single RF transmit and receive chain. The UHD driver on the host splits large transmission data streams across the two Ethernet links, sending them to the FPGA for processing. On the receive side, it similarly merges data streams coming back from the FPGA to form a continuous IQ sample stream for the host. Inside the FPGA, the split streams received over the two SFP+ ports are merged and assembled into complete IQ samples before being passed to the DAC for transmission. Conversely, on reception, the FPGA splits the ADC output streams and distributes them across the two SFP+ ports to maximize throughput back to the host server. How exactly does the FPGA automatically merge the parallel Ethernet streams from SFP+0 and SFP+1 into one logical contiguous IQ stream before sending it to the DAC? And during reception, how does it coordinate splitting the ADC output to distribute data streams efficiently across both SFP+ ports? Is this merging and splitting entirely handled by the UHD and FPGA firmware, or do we need to implement custom Python/MATLAB/C++ code to manage it?
MD
Marcus D. Leech
Wed, Jul 16, 2025 2:00 PM

On 2025-07-16 09:53, gechb21@gmail.com wrote:

The USRP X310 uses dual 10 Gigabit Ethernet SFP+ ports to support
high-throughput data transfers between the host and FPGA. I plan to
transmit and receive samples in parallel over these two SFP+ ports
using a single RF transmit and receive chain. The UHD driver on the
host splits large transmission data streams across the two Ethernet
links, sending them to the FPGA for processing. On the receive side,
it similarly merges data streams coming back from the FPGA to form a
continuous IQ sample stream for the host. Inside the FPGA, the split
streams received over the two SFP+ ports are merged and assembled into
complete IQ samples before being passed to the DAC for transmission.
Conversely, on reception, the FPGA splits the ADC output streams and
distributes them across the two SFP+ ports to maximize throughput back
to the host server.

How exactly does the FPGA automatically merge the parallel Ethernet
streams from SFP+0 and SFP+1 into one logical contiguous IQ stream
before sending it to the DAC? And during reception, how does it
coordinate splitting the ADC output to distribute data streams
efficiently across both SFP+ ports? Is this merging and splitting
entirely handled by the UHD and FPGA firmware, or do we need to
implement custom Python/MATLAB/C++ code to manage it?


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Unless there has been a change that I missed, dual-ethernet mode applies
to multiple channels.  UHD doesn't schedule packets for the same
  channel across two interfaces.

But a single 10G interface can handily handle full-rate (200Msps) for a
single channel, assuming your host is up to the task.

On 2025-07-16 09:53, gechb21@gmail.com wrote: > > The USRP X310 uses dual 10 Gigabit Ethernet SFP+ ports to support > high-throughput data transfers between the host and FPGA. I plan to > transmit and receive samples in parallel over these two SFP+ ports > using a single RF transmit and receive chain. The UHD driver on the > host splits large transmission data streams across the two Ethernet > links, sending them to the FPGA for processing. On the receive side, > it similarly merges data streams coming back from the FPGA to form a > continuous IQ sample stream for the host. Inside the FPGA, the split > streams received over the two SFP+ ports are merged and assembled into > complete IQ samples before being passed to the DAC for transmission. > Conversely, on reception, the FPGA splits the ADC output streams and > distributes them across the two SFP+ ports to maximize throughput back > to the host server. > > How exactly does the FPGA automatically merge the parallel Ethernet > streams from SFP+0 and SFP+1 into one logical contiguous IQ stream > before sending it to the DAC? And during reception, how does it > coordinate splitting the ADC output to distribute data streams > efficiently across both SFP+ ports? Is this merging and splitting > entirely handled by the UHD and FPGA firmware, or do we need to > implement custom Python/MATLAB/C++ code to manage it? > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com Unless there has been a change that I missed, dual-ethernet mode applies to multiple channels.  UHD doesn't schedule packets for the same   channel across two interfaces. But a single 10G interface can handily handle full-rate (200Msps) for a single channel, assuming your host is up to the task.