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View all threadsMake File for E310 xilinx project
Hello:
I have been unable to get a Xilinx project to make given the files in
fpga-src on github
At this time I believe that there is a problem with
uhd/fpga-src/usrp3/top/e300/zynq-ps/Makefile.srcs
In this file:
ZYNQ_PS_SRCS=$(abspath $(addprefix $ZYNQ_PS_TMP/,
hdl/e300_ps_stub.v
implementation/e300_ps.ngc \
resolves to:
/zynq-ps/hdl/e300_ps_stuv.v /zynq-ps/implementation/e300_ps.ngc
and make throws an error:
zynq-ps\Makefile.srcs:19 ... multiple target patterns. Stop.
where $(ZYNQ_PS_SRCS): is used as a target.
Searching seems to indicate that you can't have two things separated by a
space defined as a target and that is what seems to be happening here.
Although the excercise in learning about "make" syntax was useful, it would
be great if someone could clarify what should be in this file to enable it
to build a Xilinx project.
Right now I am using ISE 14.7 on Windows with the settings32.bat
environment. and at first I am just attempting to get the .xise file
generated by using the PROJECT_ONLY=1 switch
using make PROJECT_ONLY=1
from the uhd\fpga-src\usrp3\top\e300 directory.
Thanks,
Larry Van Der Jagt
Hi Larry,
We build our FPGA images in a Linux environment and do not test building
them in Windows. I'll look into this issue but in the meantime, do you have
access to a Linux system?
On Wed, Feb 11, 2015 at 2:19 PM, Larry Van Der Jagt via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hello:
I have been unable to get a Xilinx project to make given the files in
fpga-src on github
At this time I believe that there is a problem with
uhd/fpga-src/usrp3/top/e300/zynq-ps/Makefile.srcs
In this file:
ZYNQ_PS_SRCS=$(abspath $(addprefix $ZYNQ_PS_TMP/,
hdl/e300_ps_stub.v
implementation/e300_ps.ngc \
resolves to:
/zynq-ps/hdl/e300_ps_stuv.v /zynq-ps/implementation/e300_ps.ngc
and make throws an error:
zynq-ps\Makefile.srcs:19 ... multiple target patterns. Stop.
where $(ZYNQ_PS_SRCS): is used as a target.
Searching seems to indicate that you can't have two things separated by a
space defined as a target and that is what seems to be happening here.
Although the excercise in learning about "make" syntax was useful, it
would be great if someone could clarify what should be in this file to
enable it to build a Xilinx project.
Right now I am using ISE 14.7 on Windows with the settings32.bat
environment. and at first I am just attempting to get the .xise file
generated by using the PROJECT_ONLY=1 switch
using make PROJECT_ONLY=1
from the uhd\fpga-src\usrp3\top\e300 directory.
Thanks,
Larry Van Der Jagt
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hello:
Thank you for the response, I do have an Ubuntu 14.04 VM and a physical
Ubuntu 12.04 system, however, I have not gone through the pain of getting
the Xilinx tools to run on them as my experience in the past has been that
trying to run Xilinx tools on unsupported platforms can take a bit of work
to get operational.
Perhaps this has improved over the years and I may try it. An alternate
would be to build the project from scratch on the windows machine rather
than try to use make ... although that would have the downside of having
tracking any future developments being also a manual process.
At any rate, in order to further debug this issue I have added:
$(warning "source dir $(ZYNQ_PS_LIB)")
$(warning "build dir $(ZYNQ_PS_TMP)")
$(warning "zynq ps srcs $(ZYNQ_PS_SRCS)")
$(warning "base dir $(BASE_DIR)")
$(warning "build dir $(BUILD_DIR)")
$(warning "$(ZYNQ_PS_SRCS): $(ZYNQ_PS_LIB)/build_new_e300_proj.tcl
$(ZYNQ_PS_LIB)/e300_master.mhs $(ZYNQ_PS_LIB)/ps7_e300_ps_prj.xml")
To the Makefile.srcs file in the zynq-ps directory and piped the output of
make along with the warnings to a file.
The result is below:
"ISE Version: Release 14.7 - xtclsh P.20131013 (nt)"
make -f Makefile.e300.inc bin NAME=E310 DEVICE=XC7Z020 EXTRA_DEFS=""
make[1]: Entering directory
`C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300'
zynq-ps/Makefile.srcs:16: "source dir
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps"
zynq-ps/Makefile.srcs:17: "build dir
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps"
zynq-ps/Makefile.srcs:18: "zynq ps srcs
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/implementation/e300_ps.ngc"
zynq-ps/Makefile.srcs:19: "base dir
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top"
zynq-ps/Makefile.srcs:20: "build dir build-E310"
zynq-ps/Makefile.srcs:21:
"C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/implementation/e300_ps.ngc:
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps/build_new_e300_proj.tcl
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps/e300_master.mhs
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps/ps7_e300_ps_prj.xml"
make[1]: Leaving directory
`C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300'
zynq-ps/Makefile.srcs:26: *** multiple target patterns. Stop.
make: *** [E310] Error 2
Surely,
"C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v
C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/implementation/e300_ps.ngc:
is the multiple target pattern that is the problem.
Not sure exactly what the path of least pain is from here. Any ideas are
welcomed.
LVDJ
On Wed, Feb 18, 2015 at 5:50 PM, Jonathon Pendlum <
jonathon.pendlum@ettus.com> wrote:
Hi Larry,
We build our FPGA images in a Linux environment and do not test building
them in Windows. I'll look into this issue but in the meantime, do you have
access to a Linux system?
On Wed, Feb 11, 2015 at 2:19 PM, Larry Van Der Jagt via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hello:
I have been unable to get a Xilinx project to make given the files in
fpga-src on github
At this time I believe that there is a problem with
uhd/fpga-src/usrp3/top/e300/zynq-ps/Makefile.srcs
In this file:
ZYNQ_PS_SRCS=$(abspath $(addprefix $ZYNQ_PS_TMP/,
hdl/e300_ps_stub.v
implementation/e300_ps.ngc \
resolves to:
/zynq-ps/hdl/e300_ps_stuv.v /zynq-ps/implementation/e300_ps.ngc
and make throws an error:
zynq-ps\Makefile.srcs:19 ... multiple target patterns. Stop.
where $(ZYNQ_PS_SRCS): is used as a target.
Searching seems to indicate that you can't have two things separated by a
space defined as a target and that is what seems to be happening here.
Although the excercise in learning about "make" syntax was useful, it
would be great if someone could clarify what should be in this file to
enable it to build a Xilinx project.
Right now I am using ISE 14.7 on Windows with the settings32.bat
environment. and at first I am just attempting to get the .xise file
generated by using the PROJECT_ONLY=1 switch
using make PROJECT_ONLY=1
from the uhd\fpga-src\usrp3\top\e300 directory.
Thanks,
Larry Van Der Jagt
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Larry,
FWIW modern ISE/Vivado versions install out of the box without any extra work on modern Ubuntu systems…I've used 12.04/12.10/14.04 in recent years for FPGA work.
The only thing that can still be a bit of a pain is the cable driver stuff if you want to use a Xilinx USB JTAG box.
-Ian
On Feb 20, 2015, at 5:06 AM, Larry Van Der Jagt via USRP-users usrp-users@lists.ettus.com wrote:
Hello:
Thank you for the response, I do have an Ubuntu 14.04 VM and a physical Ubuntu 12.04 system, however, I have not gone through the pain of getting the Xilinx tools to run on them as my experience in the past has been that trying to run Xilinx tools on unsupported platforms can take a bit of work to get operational.
Perhaps this has improved over the years and I may try it. An alternate would be to build the project from scratch on the windows machine rather than try to use make ... although that would have the downside of having tracking any future developments being also a manual process.
At any rate, in order to further debug this issue I have added:
$(warning "source dir $(ZYNQ_PS_LIB)")
$(warning "build dir $(ZYNQ_PS_TMP)")
$(warning "zynq ps srcs $(ZYNQ_PS_SRCS)")
$(warning "base dir $(BASE_DIR)")
$(warning "build dir $(BUILD_DIR)")
$(warning "$(ZYNQ_PS_SRCS): $(ZYNQ_PS_LIB)/build_new_e300_proj.tcl $(ZYNQ_PS_LIB)/e300_master.mhs $(ZYNQ_PS_LIB)/ps7_e300_ps_prj.xml")
To the Makefile.srcs file in the zynq-ps directory and piped the output of make along with the warnings to a file.
The result is below:
"ISE Version: Release 14.7 - xtclsh P.20131013 (nt)"
make -f Makefile.e300.inc bin NAME=E310 DEVICE=XC7Z020 EXTRA_DEFS=""
make[1]: Entering directory `C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300'
zynq-ps/Makefile.srcs:16: "source dir C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps"
zynq-ps/Makefile.srcs:17: "build dir C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps"
zynq-ps/Makefile.srcs:18: "zynq ps srcs C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/implementation/e300_ps.ngc"
zynq-ps/Makefile.srcs:19: "base dir C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top"
zynq-ps/Makefile.srcs:20: "build dir build-E310"
zynq-ps/Makefile.srcs:21: "C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/implementation/e300_ps.ngc: C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps/build_new_e300_proj.tcl C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps/e300_master.mhs C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/zynq-ps/ps7_e300_ps_prj.xml"
make[1]: Leaving directory `C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300'
zynq-ps/Makefile.srcs:26: *** multiple target patterns. Stop.
make: *** [E310] Error 2
Surely,
"C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/C:/Users/vande_000/Documents/GitHub/uhd/fpga-src/usrp3/top/e300/build-E310/zynq-ps/implementation/e300_ps.ngc:
is the multiple target pattern that is the problem.
Not sure exactly what the path of least pain is from here. Any ideas are welcomed.
LVDJ
On Wed, Feb 18, 2015 at 5:50 PM, Jonathon Pendlum jonathon.pendlum@ettus.com wrote:
Hi Larry,
We build our FPGA images in a Linux environment and do not test building them in Windows. I'll look into this issue but in the meantime, do you have access to a Linux system?
On Wed, Feb 11, 2015 at 2:19 PM, Larry Van Der Jagt via USRP-users usrp-users@lists.ettus.com wrote:
Hello:
I have been unable to get a Xilinx project to make given the files in fpga-src on github
At this time I believe that there is a problem with uhd/fpga-src/usrp3/top/e300/zynq-ps/Makefile.srcs
In this file:
ZYNQ_PS_SRCS=$(abspath $(addprefix $ZYNQ_PS_TMP/,
hdl/e300_ps_stub.v
implementation/e300_ps.ngc \
resolves to:
/zynq-ps/hdl/e300_ps_stuv.v /zynq-ps/implementation/e300_ps.ngc
and make throws an error:
zynq-ps\Makefile.srcs:19 ... multiple target patterns. Stop.
where $(ZYNQ_PS_SRCS): is used as a target.
Searching seems to indicate that you can't have two things separated by a space defined as a target and that is what seems to be happening here.
Although the excercise in learning about "make" syntax was useful, it would be great if someone could clarify what should be in this file to enable it to build a Xilinx project.
Right now I am using ISE 14.7 on Windows with the settings32.bat environment. and at first I am just attempting to get the .xise file generated by using the PROJECT_ONLY=1 switch
using make PROJECT_ONLY=1
from the uhd\fpga-src\usrp3\top\e300 directory.
Thanks,
Larry Van Der Jagt
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Thanks for the response,
Based on the input I went ahead and installed ISE14.7 on Ubuntu 14.04 with
what appears to be relatively little pain ... I would still prefer to work
on the WIndows version of ISE, but "you can't always get what you want" ....
At any rate, my first cut through on running make on the Linux
implementation got much further but still fails, now the process proceeds
with various informational DRC messages from EDK until it reaches a point
where it says:
Checking platform address map ...
No changes to be saved in XMP file
Saved Make file
Xilinx Port:: Process Exec Failed:2
ERROR:EDK -
Error while running "gmake -f e300_ps.make netlist".
make[1]: ***
[/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v
] Error 1
make[1] Leaving directory
'/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300'
make: *** [E310] Error 2
I will now start digging on this but as always, any insight is welcomed.
LVDJ
Well ... perhaps this one is easier to fix than most ... since the error
indicated an issue with gmake, I did a "which gmake" and found none.
I added a symbolic link to the /usr/bin folder with sudo ln -s
/usr/bin/make /usr/bin/gmake and things seem to be progressing further.
LVDJ
On Fri, Feb 20, 2015 at 1:55 PM, Larry Van Der Jagt vandel@gmail.com
wrote:
Thanks for the response,
Based on the input I went ahead and installed ISE14.7 on Ubuntu 14.04 with
what appears to be relatively little pain ... I would still prefer to work
on the WIndows version of ISE, but "you can't always get what you want" ....
At any rate, my first cut through on running make on the Linux
implementation got much further but still fails, now the process proceeds
with various informational DRC messages from EDK until it reaches a point
where it says:
Checking platform address map ...
No changes to be saved in XMP file
Saved Make file
Xilinx Port:: Process Exec Failed:2
ERROR:EDK -
Error while running "gmake -f e300_ps.make netlist".
make[1]: ***
[/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v
] Error 1
make[1] Leaving directory
'/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300'
make: *** [E310] Error 2
I will now start digging on this but as always, any insight is welcomed.
LVDJ
Hello Again:
Just as an FYI for anyone looking at this in the future, the "make"
completed on the Ubuntu 14.04 VM with ISE 14.7 installed.
Upon completing this I copied the E300 and X300 folders that were generated
over to a the same location in the source tree on a Windows machine that
has 14.7 installed and was able to bring up the development environment
using the .xise file generated on the Ubuntu machine.
I was also able to import into PlanAhead, but needed to delete and reattach
the IP for catacodec_mmcm and axi_datamover_v3_00_a using the .xco files
that had been generated in order to get the design flow to run. The design
flow did run to completion although I have no tested the resulting .bit
file for operation.
Of course, your results may vary ....
LVDJ
On Fri, Feb 20, 2015 at 3:00 PM, Larry Van Der Jagt vandel@gmail.com
wrote:
Well ... perhaps this one is easier to fix than most ... since the error
indicated an issue with gmake, I did a "which gmake" and found none.
I added a symbolic link to the /usr/bin folder with sudo ln -s
/usr/bin/make /usr/bin/gmake and things seem to be progressing further.
LVDJ
On Fri, Feb 20, 2015 at 1:55 PM, Larry Van Der Jagt vandel@gmail.com
wrote:
Thanks for the response,
Based on the input I went ahead and installed ISE14.7 on Ubuntu 14.04
with what appears to be relatively little pain ... I would still prefer to
work on the WIndows version of ISE, but "you can't always get what you
want" ....
At any rate, my first cut through on running make on the Linux
implementation got much further but still fails, now the process proceeds
with various informational DRC messages from EDK until it reaches a point
where it says:
Checking platform address map ...
No changes to be saved in XMP file
Saved Make file
Xilinx Port:: Process Exec Failed:2
ERROR:EDK -
Error while running "gmake -f e300_ps.make netlist".
make[1]: ***
[/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v
] Error 1
make[1] Leaving directory
'/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300'
make: *** [E310] Error 2
I will now start digging on this but as always, any insight is welcomed.
LVDJ
If you're moving from Windows to Linux with your Xilinx tools, there's a
couple of caveats (which are probably not what you were seeing, but I like
to point them out as often as possible:
- Xilinx doesn't follow any standards for their shell scripts; usually, a
bash will work but they she-bang it with #!/bin/sh. On Ubuntu, for example,
this will cause the usage of a lightweight shell called 'dash', and that
won't work (dpkg-reconfigure dash will fix this at some system performance
loss) - LC_NUMERIC must be either US or C. Most European settings will cause some
tools (e.g. impact) to fail due to non-portable shell usage
Cheers,
M
On Sun, Feb 22, 2015 at 4:58 PM, Larry Van Der Jagt via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hello Again:
Just as an FYI for anyone looking at this in the future, the "make"
completed on the Ubuntu 14.04 VM with ISE 14.7 installed.
Upon completing this I copied the E300 and X300 folders that were
generated over to a the same location in the source tree on a Windows
machine that has 14.7 installed and was able to bring up the development
environment using the .xise file generated on the Ubuntu machine.
I was also able to import into PlanAhead, but needed to delete and
reattach the IP for catacodec_mmcm and axi_datamover_v3_00_a using the .xco
files that had been generated in order to get the design flow to run. The
design flow did run to completion although I have no tested the resulting
.bit file for operation.
Of course, your results may vary ....
LVDJ
On Fri, Feb 20, 2015 at 3:00 PM, Larry Van Der Jagt vandel@gmail.com
wrote:
Well ... perhaps this one is easier to fix than most ... since the error
indicated an issue with gmake, I did a "which gmake" and found none.
I added a symbolic link to the /usr/bin folder with sudo ln -s
/usr/bin/make /usr/bin/gmake and things seem to be progressing further.
LVDJ
On Fri, Feb 20, 2015 at 1:55 PM, Larry Van Der Jagt vandel@gmail.com
wrote:
Thanks for the response,
Based on the input I went ahead and installed ISE14.7 on Ubuntu 14.04
with what appears to be relatively little pain ... I would still prefer to
work on the WIndows version of ISE, but "you can't always get what you
want" ....
At any rate, my first cut through on running make on the Linux
implementation got much further but still fails, now the process proceeds
with various informational DRC messages from EDK until it reaches a point
where it says:
Checking platform address map ...
No changes to be saved in XMP file
Saved Make file
Xilinx Port:: Process Exec Failed:2
ERROR:EDK -
Error while running "gmake -f e300_ps.make netlist".
make[1]: ***
[/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300/build-E310/zynq-ps/hdl/e300_ps_stub.v
] Error 1
make[1] Leaving directory
'/home/vandel/Ettus_e310_sdk/UHD/fpga-src/usrp3/top/e300'
make: *** [E310] Error 2
I will now start digging on this but as always, any insight is welcomed.
LVDJ
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com