Poul-Henning,
I have some guesses but I look forward to others.
I think the analog multipliers are complicated in pins and support
circuitry especially if single power supply.
I used lower frequency Analog Devices units in early experimentation on the
wwvb d-psk-r.
Granted they worked. They were also pricey. But thats relative.
They can deliver gain as compared to a mixer and thats a plus.
Regards
Paul
WB8TSL

On Tue, Jan 5, 2016 at 2:56 PM, Poul-Henning Kamp phk@phk.freebsd.dk
wrote:

In message 553575724.582265.1452024437677.JavaMail.yahoo@mail.yahoo.com, Bruce Griffiths writes:

Yes, but does that really matter in this case ?

The interesting output will be coming out of a LPF so
most of the noise will die there?

--
Poul-Henning Kamp      | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG        | TCP/IP since RFC 956
FreeBSD committer      | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

In message CAD2JfAhperEkfSTG5c2U8waGkv0kY3mcbdz8w1+4J+OOaaLb2w@mail.gmail.com, paul swed writes:

The AD835 is 8-pins and as easy as they come I think.

Not needing isolation amps seems like a plus to me.

--
Poul-Henning Kamp      | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG        | TCP/IP since RFC 956
FreeBSD committer      | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

With some sine-to-square conversion as signal conditioning, not too hard
these days, this could be a relatively straight forward approach.
CERN already have digital clocks, so the DDMTD approach fits them well.

For normal mixers you want to signal condition the signal prior to the
mixers, and then signal-condition the beat notes too.

For DDMTD you do the same, but you do the post mister conditioning in
the digital domain.

I have always assumed that signal-to-noise have been the main difference
between the Gilbert cell multiplies vs. diode mixers.

Cheer1s,
Magnus

On 01/05/2016 09:19 PM, Bruce Griffiths wrote:

Mini-circuits has packaged phase detectors plug-in, surface, and with
connectors for $20 TO $70. Diode bridges with transformers. They also have
cheap wideband amps. Bet a simple DDMTD could be built with these? I know...I
wish I did have the time at present.
Happy New Year!
Don

Magnus Danielson

--
Felix qui potuit rerum cognoscere causas.
Lucky is he who has been able to understand the causes of things.
Virgil

"Noli sinere nothos te opprimere"

Dr. Don Latham, AJ7LL
Six Mile Systems LLC, 17850 Six Mile Road
Huson, MT, 59846
mailing address:  POBox 404
Frenchtown MT 59834-0404

VOX 406-626-4304
CEL 406-241-5093
Skype: buffler2
www.lightningforensics.com
www.sixmilesystems.com

On Tuesday, January 05, 2016 09:37:00 PM Poul-Henning Kamp wrote:

Bruce Griffiths writes:

Yes I believe it does as the mixer multiplier noise sets a lower limit to the
beat frequency jitter.
If only the noise from the 2 mixers were correlated then the jitter
contribution from this would largely cancel out as does the noisee
contribution of the offset oscillator.

Bruce

Poul-Henning,

On 01/05/2016 10:37 PM, Poul-Henning Kamp wrote:

You still raise the noise-level which is in the pass-band of those
filters. This will be true both for white noise and flicker noise.
The white noise will be particularly annoying as it then converts to
jitter through the slew-rate limitation as you go into the
trigger-circuit. To reduce this effect, we amplify up the signal in
steps, with higher and higher bandwidth to balance noise contribution
with slew-rate incrementation. Using noisy mixers rather than quieter
mixers makes this more worthwhile. The diode mixers needed does not have
to be very rare, just look at the 2N2222A based mixer out of NIST,
actually being a Harris chip with four transistors and a pair of off the
shelf transformers.

Yes, I've played with this, ran into the issues.
Tried to build a DTMD, but didn't manage to handle some problems before
it got side-tracked.

As always, choosing the trigg-point to have the highest slew-rate have
always been key to reducing timing jitter.k Turns out that most counters
isn't optimized for this property.

Cheers,
Magnus

Poul-Henning wrote:

You could have mentioned any of dozens of popular analog multipliers,
and the answer would have been, "because they are way too
noisy."  The AD835 is also substantially noisier than diode mixers,
but it at least begins to bridge the gap.  The folks at CERN have
been improving phase detector S/N by averaging the output of several
AD835s for the TPMON project, with promising results.  There is a
preliminary report in "EUROTeV Report 2006-005-1."

See also:

RF-based electron beam timing measurement with sub-10fs resolution,
A. Andersson and J. P. H. Sladen, CERN (EUROTeV Report 2008-015)
[phase detector with 8x AD835 analog multipliers].

ANDERSSON, A. and SLADEN, J. P. H.: "First tests of a precision beam
phase measurement system in CTF3" (Proc. PAC07).

"PRECISION BEAM TIMING MEASUREMENT SYSTEM FOR CLIC SYNCHRONIZATION,"
A. Andersson, J. P. H. Sladen, CERN (Proceedings of EPAC 2006).

Best regards,

Charles

You mean DMTD =  dual mixer time differencenotDDMTD = Digital dual mixer timer difference.The latter uses a pair of synchronisers / shift registers instead of a pair of mixers.
Bruce

On Wednesday, 6 January 2016 12:03 PM, Charles Steinmetz <csteinmetz@yandex.com> wrote:

Poul-Henning wrote:

You could have mentioned any of dozens of popular analog multipliers,
and the answer would have been, "because they are way too
noisy."  The AD835 is also substantially noisier than diode mixers,
but it at least begins to bridge the gap.  The folks at CERN have
been improving phase detector S/N by averaging the output of several
AD835s for the TPMON project, with promising results.  There is a
preliminary report in "EUROTeV Report 2006-005-1."

See also:

RF-based electron beam timing measurement with sub-10fs resolution,
A. Andersson and J. P. H. Sladen, CERN (EUROTeV Report 2008-015)
[phase detector with 8x AD835 analog multipliers].

ANDERSSON, A. and SLADEN, J. P. H.: "First tests of a precision beam
phase measurement system in CTF3" (Proc. PAC07).

"PRECISION BEAM TIMING MEASUREMENT SYSTEM FOR CLIC SYNCHRONIZATION,"
A. Andersson, J. P. H. Sladen, CERN (Proceedings of EPAC 2006).

Best regards,

Charles

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In message 568C46B9.4020303@rubidium.dyndns.org, Magnus Danielson writes:

Digitize the LPF output and do a curve-fit to find the zero-crossings ?

--
Poul-Henning Kamp      | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG        | TCP/IP since RFC 956
FreeBSD committer      | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

Hi Poul-Henning,

On 01/06/2016 12:28 AM, Poul-Henning Kamp wrote:

That would work. You could least-square fit it with very cheap
processing. The LPF would mainly need to reject the sum frequencies to
act as anti-aliasing filter, and the noise would be filtered out by the
least-square processing.

Estimating the phase and slew-rate, and then use those to calculate the
actual through-zero phase would not be too hard. As a consequence you
get a slew-rate monitor, which act as an observation of signal level.

Cheers,
Magnus

Hi

Ok, so what needs to be done with the output of the mixer (no matter how you do it)?

Assume you start from 10 MHz and head down to 10 Hz.

Assume you are mad at your 5370 and want significantly better performance.

Where does that get you?

The 5370 already is in the ~ 20 ps range. A lot depends on your definitions and
how good your sample is running. Let’s call that 2x10^-11 at tau = 1 second. You
could indeed call it a couple of other things as well.

Simply moving up a decade with a whole bunch of gear and it’s limitations seems like
a waste. To me you want to go for 1 to 2x10^-13 as your target. It is an achievable target
and there are a number of papers that validate it as a reasonable DMTD target.

You get a 1x10^6 “amplification due to your down mix from 10 MHz to 10 Hz. You then
need another 1x10^7 to get you to your target. All errors from everything included, you need to
work out the location of the zero crossings to within 100 ns.

The practical examples of doing it include some fairly tight lowpass filtering as well as high
pass filtering ahead of the detection process. I have never seen it done without this filtering
as part of the setup. There is just to much noise at the detector otherwise. Most systems
have something like a 15 Hz lowpass and a 5 Hz high pass for a 10 Hz note.

With fairly good diode ring phase detectors and a less than perfect (not 25 stage Collins style)
analog limiter, you can indeed get to the target.

Doing it digitally assumes you have a pretty good clock and sampler. If you look at it as a
3V p-p triangle waveform at 10 Hz, you have a 60V / second slew rate. (a 1 V p-p sine wave
is pretty close to the same number). You need to filter that at 15 Hz and then resolve it to about
6 uV at the zero crossing. You can either keep a high sample rate and make your filter a
major nightmare or you can decimate ahead of the filter and turn the resolver into a headache.
Either way, there is some work to be done.

A couple of op-amp packages is about all it takes to do the limiter with the analog approach ….

Bob

On 1/5/2016 12:07 PM, Bruce Griffiths wrote:

Read Gilbert's paper or Gray and Meyers analog IC textbook and
you will see that the whole theory of operation of these
depends on keeping the signal levels in them very small,
especially if linearity (actually translinearity) is
important.  They always have current sources in the
emitters that contribute a lot of noise.  So you have
small signals and large noise.  The IC's that are
designed to be DC coupled have even more sources of
extra noise.

IMHO, they only make sense in low performance applications
where the lack of transformers is important or in DC
coupled applications.  The only time I have used an
analog multiplier IC was in Costas loop to demodulate
QPSK from weather satellite.  It needed to be DC coupled.

Rick Karlquist N6RK

On Wed, 6 Jan 2016 18:30:07 -0800
"Richard (Rick) Karlquist" richard@karlquist.com wrote:

How about using the Gilbert Cell as "digital" mixer,
ie driving the currents hard from one branch to the other
and replacing the current sources by resistors?

How much would that improve the noise? Would it be still much
worse than the diode mixer?

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

On 2016-01-07 13:35, Attila Kinali wrote:

I think so.

I checked up the MC1496 (just a sample-point of a classic Gilbert cell
chip), it has 25 mV Peak, or -22 dBm as maximum input voltage before it
starts to compress. Looking at the VCWR curves it is clear that it
starts to misbehave there.

Comparing that to the SBL-1+ double-balanced mixer (another random
sample-point), which has an LO max of +7 dBm, you are looking at a
difference of about 30 dB (29 to be exact, but neither number is exact
to the 1 dB so).

The MC1495, which is a linearized variant of the MC1496 (only true to
some degree, it's more complex than that), allows 5 V signals easily,
but internally you then go down to about the same levels.

So, while you can drive things harder, you can do that on both sides. If
it where less of a difference I'd say it would not be such a big
difference, but it is relatively large difference here.

Anyway, just wanted to put a few numbers down to illustrate the
difference.

Cheers,
Magnus

On 1/7/2016 4:35 AM, Attila Kinali wrote:

You can drive the Gilbert cell as hard as you want, but
the active region is only about 100 mv so the extra
drive voltage doesn't help.  It is the same as if you
drove it with a 100 mV square wave.  Somewhat better
than a sine wave, but not a game changer.

You can of course try to replace the emitter current source
with a resistor, which works to the extent that you can
afford to throw away voltage across the resistor, but
you will never get a very high impedance.  No OTS IC's
are designed this way.  What would be better would be
to use an inductor.  A true noiseless current source.
Again no OTS IC's are designed this way.

You would have to homebrew the whole mixer from discretes.

Rick Karlquist N6RK

Gilbert cells are very useful in many "compromise" circuits. If you have a
fixed power budget on the very low end, Gilbert cells may be the best
choice because they make a balanced mixer stage that has substantial gain
with miniscule LO drive requirements.

Contrast that with a DBM diode mixer where they take substantial LO drive
and operate some loss.

In the no-compromise time-nuts context, there may be a good place for a
Gilbert cell. Maybe in a circuit where the Gilbert cell is getting hit with
a well-defined signal with low dynamic range that dwarfs the noise
contribution. The low LO requirement of a Gilbert cell also makes it easier
to isolate the LO from the rest of the circuitry and that can reduce
shielding needs. But it's not gonna go where you need both low noise and
high dynamic range.

Tim N3QE

On Wed, Jan 6, 2016 at 9:30 PM, Richard (Rick) Karlquist <
richard@karlquist.com> wrote:

Hi

If your intention is to run a mixer with saturated inputs …. just run
an X-OR gate. It will handle the high level signals much better than
an over-driven analog part.

Yes somebody should check out a board built that way …. I’ll
let you know when I do.

Bob

On 1/7/2016 3:11 PM, Bob Camp wrote:

If you look at the schematic of an XOR gate IC and compare it
to the schematic of, for example, an MC1496 mixer, you will
see a lot of similarity.  If the gate is of the ECL type,
it will have the addition of emitter followers, but that
it a minor detail of implementation.  I'm not sure there
is a huge difference.  ECL is a great logic family in
general (self-confessed ECL-phile here :-) but it is
probably the worst for phase noise, compared to the
saturating logic types.

Rick Karlquist N6RK

Hi

The board I have uses high speed CMOS single gate XOR’s. They have a pretty good
phase noise floor (-170’s) so they should be pretty reasonable.

Bob

Hi Bob,
In some article, I see people use a D-flipflop to sample the input
signal with reference clock. When you want implement a mixer what's the
difference between D-flipflop and XOR gate? Acorrding to my understanding,
to multiply 1bit with another, I should use an AND gate, right?
When you refer high speed CMOS XOR gate, do you mean 74LVC1G86?

Thanks

BI7LNQ

2016-01-09 6:42 GMT+08:00 Bob Camp kb8tq@n1k.org:

Hi

You can use a D flip flop to sample (down convert) a signal. You may or
may not get into metastability problems when you do.

If you treat the gate inputs as -1 and +1 rather than 0 and 1, the XOR is a
multiplier. If you put two signals into the gate and look at the output on a
spectrum analyzer, you get the expected multiplier output. The why of
the -1 and +1 stuff is something I will leave to others. It’s a bit involved.

The 74LVC is a good series to use. The NC7SZ series is also a good one.
In both cases, you will get a better noise floor at 5.5 V than at 3 V.

Bob

On Sat, 9 Jan 2016 10:19:05 +0800
Li Ang lllaaa@gmail.com wrote:

A D-Flipflop is a rather weird mixer. I have not done the calculation,
but i'm pretty sure that the output is not exactly what you'd expect
it from a normal mixer (namely having half the energy at the frequeny
difference and half at the sum).

An XOR gate on the other hand, produces a very nice spectrum, given
you input two clean square wave signals.

If you think of the signals as digital in the computational sense,
with "high" representing "1" and "low" representing "0" then yes.
But in signal theory, it's more appropriate to think of signals
as "high" representing "+1" and low representing "-1".
In the latter case, the XOR is the multiplicative element, and not
the AND gate.

Generally speaking: Faster CMOS better than slower CMOS in terms of phase noise.
(Though, I have yet to see actual measurements of this)

Single gate chips better than multi gate chips.
(no interference through the power supply of the different sub-parts)

			Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Attila,

On 01/09/2016 09:25 PM, Attila Kinali wrote:

It's not that wierd. It's a sampler, and thus it acts like a mixer as if
the signal is spikes, which is just another interpretation of the
Nyquist frequency aliasing. Meta-stability however creates an
"interesting" aspect.

Indeed.

An interesting variant of the XOR gate as being used as a mixer is when
you build a rubidium. One synthesis approach being used is to divide the
5 MHz OCXO signal with 16 to get 312,5 kHz. Then XORing it with 5 MHz
produces as one of it's mirror signals 5,3125 MHz which is then fed with
a step-up signal of 60 MHz or 90 MHz into the SDR diode in the cavity.

A third digital phase-detector is the SR flip-flop. It avoids the 180
degree phase property (really a triangle wave signal) of the XOR, but
give a 360 degree phase sawtooth. This can be helpful in certain lock-up
conditions.

The phase-frequency detector of the 4046 and the like has additional
flip-flops to remember slipped cycles and forcing the frequency to
regain that. Those provide a strong frequency lock mechanism with a
phase detector in one.

Well, you should wire the other parts into passive mode.

Cheers,
Magnus

In message 20160109212523.39180e2b7a788fe1ee2d7a3a@kinali.ch, Attila Kinali
writes:

Would paralleing multiple gates in the same chip make things
better or worse ?

--
Poul-Henning Kamp      | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG        | TCP/IP since RFC 956
FreeBSD committer      | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

Hi

The gotcha is that each family gets measured as the parts come out. Thus the data
is spread out over about a 40+ year period. Most of it was taken down in log books
off of a screen ….

Bob

God morgon,

On Sat, 9 Jan 2016 23:01:31 +0100
Magnus Danielson magnus@rubidium.dyndns.org wrote:

Ah right! That also explains my uneasy feeling about it :-)

It's relatively easy to get around metastabilitiy: just add another
couple of D-flipflops in series. Unfortunately, that will only fix
the metastable lingering in-between. It wont fix the edge being at
the wrong time.

SR-flipflop? Are you refering to the JK-FF phase detector or the PFD?

Interesting... i have to look into the old datasheets.

That would be a waste of good PCB space ;-)

			Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Moin phk!

On Sat, 09 Jan 2016 22:56:27 +0000
"Poul-Henning Kamp" phk@phk.freebsd.dk wrote:

Good question. I have no idea.

My first guess would be, that it would only give a slight improvement,
if at all.

The reasoning is the following:
Under the assumption that the noise of all gates is ergodic and stationary,
then averaging the outputs of the gates should reduce the output noise.

But the noise is not truly ergodic and there will be coupling between the
gates (both through the power supply and the outputs), that will change the
noise properties of the gates. Which in turn might lead to positive interference
of the noise, instead of averaging out.

But I have to admit that noise in electronic circuits is for me still
something very unintuitive. And I am more often wrong than right, when
it comes to predicting noise behaviour.

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

God eftermiddag,

On 01/10/2016 11:21 AM, Attila Kinali wrote:

Indeed. The second DFF will reduce the noise induced by the
meta-stability. A small average shift in phase due to average
meta-stability time-shift isn't usually a bit problem.

However, it's down-mixing abilities is relatively straight-forward.

A straight SR-flipflop. I would have written JK-FF or PFD if I meant it.
Also, as I mentioned the PFD directly after, you could have concluded
that was not what I intended.

A SR-flip-flop with no illegal input states is easy to build from a 74HC00.

It's really several SR flip-flops interconnected. It's intended to
simplify design with a "digital" core, it aids in frequency lock as it
pulls the integrator cap in the right direction stronger than the weak
beating does on a distance in frequency difference. This way, you
improve locking time for simple designs. There is other ways to aid the
loop known to the professional.

No. If you add noise through the other parts of the same chip, you will
waste more PCB space to work around it.

Cheers,
Magnus

On 01/10/2016 11:32 AM, Attila Kinali wrote:

Signals couples so nicely through power-pins, as the parasitic
inductance work on them. This is also known as ground-bounce. It will
limit the properties, and already have. In some counters, it was
"convenient" from a layout perspective to use a double-comparator. The
ground-bounce formed one of the main limiting factors, so in the next
generation they used single comparators and a few other tricks and could
half the noise-limits of the counter.

Few "chips" (rather chip packages) includes internal decoupling caps,
but it has started to appear for some of the larger onces as it is the
only way to avoid the issues while pushing speed upwards.

If you feed the same signal to the different XOR gates in the same
package, wiring might cause some spread, but ground-bounce would connect
them such that "late" gates would be encouraged by "early" gates. It
will not be so "independent" anymore.

Sometimes this cross-talk can work for you, but often against you.
Unless you know exactly what you are doing, isolation is a good thing.

Cheers,
Magnus

Hi

How do the gate outputs combine?

Often the “pull down” part of the gate is stronger than the “pull up” part of the gate.
If that’s what happens, you get an odd voting process rather than an average ….
( one gate says low, two gates say high, we go low ….)

Bob

On Sun, 10 Jan 2016 14:30:41 +0100
Magnus Danielson magnus@rubidium.dyndns.org wrote:

The illegal input states were my concern, indeed. And a quick google
didn't show up anything to disperse these....not until I started reading
the 4046 datasheet in detail.

But there is one thing about the arangement of the SR FF in the 4046[1]
that bothers me:
Although S = R = 1 is valid, it does lead to the output oscillating
between 0 and 1.

		Attila Kinali

[1] Ti CD74HC4046A Datasheet
http://www.ti.com/lit/ds/symlink/cd54hc4046a.pdf

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

"generate stable high -frequency signals  with d flip-flops as digital
mixers ans all -IC low frequency phase -locked loop", by R.Treadway and
L.J. Reed, page 78 Electronic design 1 January 1972
Resistot array denounces D flip-flop  mixer page 184 EDN 12 April 1990
digital frequency subtract or  EDN 1 April 1981
Kamil Kraus: Die Arbeitsweise eines einfachen Digitalmischer, Seite 72
Elektronik Heft 24, 1980 a very good explanation of the function of the
digital mixer-- in German
Design ideas; D flip-flop sutracs frequencies by Richard Kochis,
Hewlett-PackardCo Ft. Collins ,CO, Gerald Flachs , New Mexico State
University, Las Cruces, END 15 April, 10981 page 149
Robert a Pease National Semiconductor Corp : Four ICs subtract
frequencies, EDN 1 April 1981
"Digitalis keverofokozat tervezese",  Zombay Frerenc, Radiotechnika,
Seite 244 # 5 1996,  a complete design of the digital mixer with
detailed theory and example in three consecutive issue of the magazine
Radiotechnika -- in Hungarian.
By using that literature I designed many frequency synthesizers
containing D flip-flops as a digital mixer

73
KJ6 UHN
Alex
[alias Dr.Dipl.Ing. Alexander Pummer, PCS Consultants]
US patents:  many if you are interested I will send you a list

On 1/10/2016 10:56 AM, Attila Kinali wrote:

and there was also a frequency/phase detector from Analog Devices, which
took care about that dead zone
73
KJ6UHN
Alex

On 1/10/2016 10:53 AM, Richard (Rick) Karlquist wrote:

Am 10.01.2016 um 22:47 schrieb Alexander Pummer:

AD9901.

73, Gerhard, DK4XP