Hello,

I am currently trying to design my own OOT module, yet when I run ‘make testbenches’ I get the following error…

ERROR: [VRFC 10-2063] Module <rfnoc_block_trigger> not found while processing module instance <dut> [/workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/rfnoc_block_trigger_tb.sv:123]

ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

However, it appears to have been found and added according to the console…

BUILDER: Adding Verilog : /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/rfnoc_block_trigger.v

BUILDER: Adding Verilog : /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/noc_shell_trigger.v

BUILDER: Adding Verilog : /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/rfnoc_trigger.v

BUILDER: Adding Verilog : /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/rfnoc_trigger_regs.vh

I am wondering if anyone else has come across this and if so how to fix it.

Thanks

Joe

I found explicitly including the verilog in the testbench using “`include” worked. However, I found it to be the case that for any module that is needed, even if it was “added” by the builder.

I am currently trying to trace through the makefiles to see what is wrong, but it seems it can not find any sources unless explicitly told. I could go through the process of manually including every file needed, however, I feel like this would be inefficient in the long run, so I am still trying to solve what is causing this.

It seems every module that is needed is in fact added by the builder, but for whatever reason it can not be found.

Here is the updated error report…

ERROR: [VRFC 10-2063] Module <synchronizer> not found while processing module instance <sync_ctrl_i> [ /workarea/uhd/fpga/usrp3/lib/rfnoc/core/backend_iface.v:69]

ERROR: [VRFC 10-2063] Module <pulse_synchronizer> not found while processing module instance <soft_ctrl_rst_sync_i> [ /workarea/uhd/fpga/usrp3/lib/rfnoc/core/backend_iface.v:81]

ERROR: [VRFC 10-2063] Module <pulse_stretch_min> not found while processing module instance <soft_ctrl_rst_stretch_i> [ /workarea/uhd/fpga/usrp3/lib/rfnoc/core/backend_iface.v:91]

ERROR: [VRFC 10-2063] Module <ctrlport_endpoint> not found while processing module instance <ctrlport_endpoint_i> [ /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/noc_shell_trigger.v:173]

ERROR: [VRFC 10-2063] Module <ctrlport_to_settings_bus> not found while processing module instance <ctrlport_to_settings_bus_i> [ /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/rfnoc_block_trigger.v:200]

ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds

INFO: [USF-XSim-99] Step results log file:' /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/xsim_proj/xsim_proj.sim/sim_1/behav/xsim/elaborate.log'

ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or ' /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/xsim_proj/xsim_proj.sim/sim_1/behav/xsim/elaborate.log' file for more information.

ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2495.422 ; gain = 0.152 ; free physical = 12659 ; free virtual = 26860

ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

And here is the modules I have manually include(so far),

Inside rfnoc_block_trigger_tb.sv, I put the following include statements,

`include " /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/rfnoc_block_trigger.v"

`include " /workarea/uhd/OOTs/rfnoc-trigger/fpga/rfnoc_block_trigger/noc_shell_trigger.v"

`include " /workarea/uhd/fpga/usrp3/lib/axi4s_sv/AxiStreamIf.sv"

`include " /workarea/uhd/fpga/usrp3/sim/rfnoc/sim_clock_gen.sv"

inside noc_shell_trigger.v, I put the following include statements

`include " /workarea/uhd/fpga/usrp3/lib/rfnoc/core/backend_iface.v"

I have checked for typos, and I have found none.