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Discussion of precise time and frequency measurement

Locking 100 MHz to 10 MHz

Matt Ettus

Wed, Dec 19, 2007 6:36 PM

I am designing a system where I lock a 100 MHz VCXO to a 10 MHz
reference using an AD9510 clock PLL chip. I have two questions to
which I don't know the answer:

First, given the specs of both oscillators, I know how to choose the
right loop bandwidth. The problem is that I have no idea what kind of
10 MHz oscillators people are going to connect. The 100 MHz osc
typical specs for phase noise are:

10Hz -65dBc
100Hz -68dBc
1k -98
10k -140
100k to 100MHz -145

I was thinking of just going with a 1kHz bandwidth, for lack of any
better ideas.

Second, for when there is no 10 MHz reference connected, the system
needs to be brought to a reasonable frequency. The PLL charge pump
outputs are tri-stated. On the end of the loop filter, right before
the control voltage input to the VCXO, I have a resistor divider to
center the voltage between 3.3V and ground. I use 100K resistors in
the hope that they will not affect things when the loop is active, but
I can't really tell, since all the phase noises involved are well
below the ability of my equipment to measure. Is this a safe
technique, or am I messing up the performance while the loop is
locked?

Thanks,
Matt

I am designing a system where I lock a 100 MHz VCXO to a 10 MHz reference using an AD9510 clock PLL chip. I have two questions to which I don't know the answer: - First, given the specs of both oscillators, I know how to choose the right loop bandwidth. The problem is that I have no idea what kind of 10 MHz oscillators people are going to connect. The 100 MHz osc typical specs for phase noise are: 10Hz -65dBc 100Hz -68dBc 1k -98 10k -140 100k to 100MHz -145 I was thinking of just going with a 1kHz bandwidth, for lack of any better ideas. - Second, for when there is no 10 MHz reference connected, the system needs to be brought to a reasonable frequency. The PLL charge pump outputs are tri-stated. On the end of the loop filter, right before the control voltage input to the VCXO, I have a resistor divider to center the voltage between 3.3V and ground. I use 100K resistors in the hope that they will not affect things when the loop is active, but I can't really tell, since all the phase noises involved are well below the ability of my equipment to measure. Is this a safe technique, or am I messing up the performance while the loop is locked? Thanks, Matt

Bruce Griffiths

Wed, Dec 19, 2007 7:56 PM

Matt Ettus wrote:

Second, for when there is no 10 MHz reference connected, the system
needs to be brought to a reasonable frequency. The PLL charge pump
outputs are tri-stated. On the end of the loop filter, right before
the control voltage input to the VCXO, I have a resistor divider to
center the voltage between 3.3V and ground. I use 100K resistors in
the hope that they will not affect things when the loop is active, but
I can't really tell, since all the phase noises involved are well
below the ability of my equipment to measure. Is this a safe
technique, or am I messing up the performance while the loop is
locked?

Thanks,
Matt

Matt

Use an SPDT analog switch to connect the 100MHz EFC to either the PLL
filter output or to whatever voltage required to centre the 100Mhz
oscillator frequency.
Could be a low impedance pot, resistive divider DAC output etc. Use
large C to ground at pot wiper (or divider tap) to minimise noise.
Use a diode detector and a comparator to check if the external 10MHz
input is present.
If the 10MHz is present switch the EFC input to the filtered PLL ouput.
If the 10MHz signal isnt present switch the EFC to the filtered divider
(or pot wiper or DAC) output.

Buce

Matt Ettus wrote: > - Second, for when there is no 10 MHz reference connected, the system > needs to be brought to a reasonable frequency. The PLL charge pump > outputs are tri-stated. On the end of the loop filter, right before > the control voltage input to the VCXO, I have a resistor divider to > center the voltage between 3.3V and ground. I use 100K resistors in > the hope that they will not affect things when the loop is active, but > I can't really tell, since all the phase noises involved are well > below the ability of my equipment to measure. Is this a safe > technique, or am I messing up the performance while the loop is > locked? > > Thanks, > Matt > > Matt Use an SPDT analog switch to connect the 100MHz EFC to either the PLL filter output or to whatever voltage required to centre the 100Mhz oscillator frequency. Could be a low impedance pot, resistive divider DAC output etc. Use large C to ground at pot wiper (or divider tap) to minimise noise. Use a diode detector and a comparator to check if the external 10MHz input is present. If the 10MHz is present switch the EFC input to the filtered PLL ouput. If the 10MHz signal isnt present switch the EFC to the filtered divider (or pot wiper or DAC) output. Buce