Another interesting influence is the number of outputs that are switching and
the load on them.  In particular, if you have several outputs running at
different frequencies, the clock-out delay should be slightly longer when 2
outputs switch when compared to when only one is switching.

Has anybody measured that on a PIC? (or similar chip)

I think one of tvb's picDEVs has several outputs.

--
These are my opinions.  I hate spam.

On Fri, 07 Jan 2022 12:40:49 -0800, you wrote:

To some extent:
https://www.eevblog.com/forum/projects/easiest-way-to-divide-10mhz-to-1mhz/msg3257018/#msg3257018

That entire thread is full of misinformation and should be ignored unless one understands the difference between random and data dependent jitter.

For a well designed divider with a single output frequency only the random jitter spec is significant.

One doesn't need a bunch of expensive LeCroy gear to measure RJ of such dividers as its PN manifestations are readily apparent and measurable.

Using one of the supposedly super low jitter flipflops isn't a panacea. In practice unless an appropriately designed ZCD is used the wideband input noise of the very fast FF will dominate and produce much more jitter than expected due to the relatively slow slew rate of the outputs of most 10MHz sources.

Bruce

All -- The 2012 test results for the T2-mini, which contains a PIC
divider chip, is here:

http://leapsecond.com/pic/jitter/

It's about 1 ps, or sqrt(2) less because it was comparing two T2-mini
against each other with a common reference. Also note that this
measurement is the sum total of the Wenzel sine-to-square circuit
onboard the T2mini, the PIC divider chip itself, and the 74AC04 buffer chip.

I also included some plots of a baseline test to show that the Wenzel
ULN (Ultra Low Noise) reference and the Miles' TimePod analyzer are not
the limiting factor in the test.

Hal -- The pD17 PIC divider used in the T2-mini has a single output. See
T2-mini schematic in the above URL. The PIC code is here:

http://leapsecond.com/pic/src/pd17.asm

Bruce -- I agree with your comments. Thanks for posting that.

Attila -- I have not measured the voltco. Note the T2-mini has an
onboard regulator. I also have not measured tempco. Although the jitter
is about 1 ps the wander over that 10 minute run is about ±6 ps (2.4 ps
rms). Look at the phase plot in the test results. This is also why the
ADEV plot has that characteristic plateau from tau 2 to 20 s.

IIRC, the test was done causally on a floor in open air so walking,
breathing, drinking coffee, and checking email are known to wiggle
things at the picosecond level. Someone could look into this more if
they wish. I would be interested to know how much of the wandering is
due to the voltage regulator vs. Wenzel transistor circuit vs. the PIC
vs. the 74AC chip.

/tvb

On 1/7/2022 12:40 PM, Hal Murray wrote:

On 1/7/2022 5:00 PM, Bruce Griffiths wrote:

Tom

The voltage coefficient of delay for a 74AC04 is around -300ps/V so with a tempco of -1.1mV/k for the output of a 7805 this results in an induced delay tempco of around +0.33ps/K for the 74AC04 due to the voltage regulator tempco. The typical propagation delay of the 74AC04 is around 4ns with an associated tempco of around 12ps/K. Thus the actual propagation tempco dominates over induced tempco. I would expect a similar result for the PIC clock to output propagation delay.

Bruce

Would an « AVRDIV » have similar performances, with similar 8 pins processors such as the Attiny13a ?
Advantage : it features one cycle instructions, so possible to divide by many other factors (including odd numbers)
GC

On Fri, 7 Jan 2022 19:05:58 -0800
Tom Van Baak tvb@LeapSecond.com wrote:

I can't seem to find the phase plot you mention.

But I think the culprit here is not the PIC but the sine-to-square wave
converter at the input. The design is quite sensitive and needs a nice
environment to perform well.

Attached is my version of the design, trying to improve on it.
(ignore the double resistors in parallel and series. I used those
to keep the BOM small for production)

First improvement is to make the circuit symmetric. A lot of variability comes from
the asymmetry of the two branches. Thus making everything symmetric improves stability
and decreases noise.

Second improvement is to stabilize the current through the circuit using a current
mirror. This alone reduces the sensitivity to supply voltage variation by a factor 4.
Further improvment can be made by using an opamp based current source with a stable
and low-noise voltage reference.

Third improvement is to replace the input inductor by a proper filter.
I figured out that the inductor in itself doesn't do much for filtering
as its impedance at the relevant frequencies is too low. Changing it to
a proper LC filter helps quite a bit. Additionally, adding a damping element
(R801/802, C803/804) reduces resonances and thus further improves PSRR.
The weird looking capacitor C801 is a pass through capacitor. A normal
ceramic capacitor should work equally well here. Also note that the start
of winding of the inductor is facing the diff-pair. This is in order to
minimize coupling noise into the inductor.

Forth improvement is to use a second stage, thus applying Collins [1,2]
lessons to the circuit. It also allows to use differential output from
the diff-pair amplifier, further increasing PSRR. The choice of comparator
chip is, as far as I can tell, not critical. I choose the LTC6752 because
it works down at 4V (actually 2.45V) and has a seperate supply for the output.
I switched hysteresis off to remove one noise term [3] as the input slew rate
is fast enough, but I doubt it makes much of a difference.

Fifth improvement is to make the supply low voltage. The design here is done for 4V
in order to be able to power everything from USB. The design does work at 5V as well.
Only change I'd do is to increase the 200Ω resistance in the current mirror (R807/808)
to 270-300Ω.

Unfortunately, I did not have the possiblitiy to measure and characterize this circuit.
If you have some time to spare, I would welcome some measurements.
Also feel free to critizise my circuit. I would love to hear how it could be further
improved.

I noted a valid input power range. The lower end is limited by the gain of the
diff-pair and its ability to increase the amplitude enough to drive the comparator
properly. The upper end is limited by the collector-emitter voltage seen by the
diff-pair. Above 16dBm the transistors start to saturate and the linearity drops.
At 20dBm the base goes to negative voltages and weird things start to happen.

Another thing to note is, that the slope-gain of the diff-pair changes with input
power. And with the slope-gain also the delay through the circuit. Or in other
words, there is some AM to PM conversion. Thus you should ensure that the input
amplitude is as constant as possible. I don't remember whether I characterized
this, though. So I don't know/remember how big the effect is.

If you build this circuit, please note that the two filter capacitors for the
comparator are NFM21PS106B0J3 from Murata. They have very good high-frequency
characteristics. If you use other capacitors, you will need to stagger them
as 10µF, 1µF 100nF, 10nF to get the same performance. Though starting at 10µF
is probably overkill and starting from 1µF should be enough.

			Attila Kinali

[1] The Design of Low Jitter Hard Limiters, by Collins, 1996

[2] A Fresh Look at the Design of Low Jitter Hard Limiters, by yours truly, 2019
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2019_collins_isf.pdf

[3] A Physical Sine-to-Square Converter Noise Model, by yours truly, 2018
http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes

Hi

There are a lot of different 78x05 devices out there and various outfits
pay more or less attention to the tempco on various die shrinks / redesigns.
You can see a wide range of temperature performance ( > 10:1) between
different examples from vendor A vs vendor B.

With any linear regulator, self heating can degrade the “input side” rejection.
Since there are lots of ways to load a regulator, this just piles in on top of the
tempco stuff.

If the 74AC04 is the dominant source of error (and I’m not at all sure it is),
there are chips with significantly lower propagation delay. Has your 74AC04
been through a shrink that cuts it’s delay in half? Who knows …. Who’s
“king of the hill” this month? Buy a bunch of chips and test them.

It all gets really tangled …...

Bob

Maybe it got mashed up, but I only linked to one post, and that
addressed the specific question that had been asked. There is also, as
far as I know, no 'misinformation' in it. However if anything does
need corrected, I can easily do that.

One of the main reasons that I did the test was all the actual
(IMHO...) misinformation that was in the thread about the PIC
dividers. I find them very useful and have not had any problems with
them, but since they are mostly used on 53131As which do not have a
very high resolution, I also wanted to see if I was missing anything.

As far as I can see, it showed just what is going on as well as I
could have expected with that scope, os I don't quite agree that
everything should be ignored :)

Angus.

On Sat, 8 Jan 2022 14:00:28 +1300 (NZDT), you wrote: