usrp-users@lists.ettus.com
Discussion and technical support related to USRP, UHD, RFNoC
View all threadsMultiple DDCs for a single radio channel
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing tests
with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
I have seen that application will only allow a number of 10 custom blocks
on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing tests
with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
Hello Carlos,
Correct, you can only have 10 custom blocks currently. There is also a
limit to the amount of data that can pass into and out of a block, the
crossbar can't move 1600 MS/s out of a single block for instance. What is
your application requirement? If you need to pick out 8 independent blocks
of bandwidth by doing eight separate frequency shifts and decimations then
I suspect you will encounter resource limits in the FPGA. There have been
two implementations of polyphase filter banks to channelize the spectrum,
but I don't know the details of their features. It may be worth looking
into as a more resource efficient means of achieving your needs. The total
sample rate will need to be less than 400 MS/s in order to be carried over
the two 10 Gigabit Ethernet links.
If you can describe your application needs a bit more we may be able to
offer more advice.
Regards,
Derek
On Thu, Apr 26, 2018 at 8:58 AM, Carlos Alberto Ruiz Naranjo via USRP-users
usrp-users@lists.ettus.com wrote:
I have seen that application will only allow a number of 10 custom blocks
on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing tests
with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Carlos,
Unfortunately no -- that's not possible :)
A few reasons:
- As you've mentioned, there's an RFNoC CE limit... The generator refuses
to insert more than 10, but fundamentally I believe it's 16 total CEs
possible, so you get 14-15 usable CE spots depending on how many radio
blocks are instantiated. So you cannot actually create an FPGA image that
has the required blocks - I believe the sample rate on the RFNoC radio for X310 cannot be set to
32 kHz... the master_clock_rate has only a few predetermined values, so
you'll need to set the rate on the RFNoC: Radio to one of those clock rates
(otherwise it will coerce it for you).
The follow up suggestion of one DDC with 8 inputs and 8 outputs might work.
One more thing to consider would be that the total IO rate (data rate * num
ports) of a single CE has to be less than 2x the clock rate of the CE--
this is because the CE shares the crossbar connection between all ports,
and the crossbar uses a 64 bit bus instead of 32 bits. For this particular
scenario, I might recommend an architecture like this...
Radio (high mclk) ==> single channel DDC (downsample by 32x or something)
==> Splitstream with 8 output ports ==> DDC with 8 input/output ports
For the DDC, there's a verilog parameter you can change that adds more
channels -- I believe it defaults to 2. You'll also want to change the NOC
ID of the updated DDC so you can create a new xml definition with 8 ports,
and then probably edit the gr-ettus block to provide 8 ports, too.
For the Splitstream, you may need to copy the existing block and create a
version that has 8 ports. I'm not sure off the top of my head but I think
it only provides 2 outputs.
Alternatively, you could investigate the rfnoc polyphase channelizer :) I
saw some activity back in February but not sure about current status.
Hope this helps,
EJ
On Thu, Apr 26, 2018, 4:00 AM Carlos Alberto Ruiz Naranjo via USRP-users <
usrp-users@lists.ettus.com> wrote:
I have seen that application will only allow a number of 10 custom blocks
on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing tests
with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hello,
thank you Derek and Ej. I am already beginning to understand what my
limitations are going to be.
I want channalizer in 8+8 variables and not evenly spaced channels. Then I
think that I cant use the rfnoc polyphase filter. The channels will be
processed independently on my computer.
This is my ideal scenario:
If I use a single DDC for radio channel (1:8) my IO rate is 100Mhz +
8x600Khz = 104.8Mhz, right? Then I need a CE clock rate > 209.6Mhz? Would
it be possible?
Thank you.
2018-04-26 12:26 GMT+02:00 EJ Kreinar ejkreinar@gmail.com:
Hi Carlos,
Unfortunately no -- that's not possible :)
A few reasons:
- As you've mentioned, there's an RFNoC CE limit... The generator refuses
to insert more than 10, but fundamentally I believe it's 16 total CEs
possible, so you get 14-15 usable CE spots depending on how many radio
blocks are instantiated. So you cannot actually create an FPGA image that
has the required blocks - I believe the sample rate on the RFNoC radio for X310 cannot be set to
32 kHz... the master_clock_rate has only a few predetermined values, so
you'll need to set the rate on the RFNoC: Radio to one of those clock rates
(otherwise it will coerce it for you).
The follow up suggestion of one DDC with 8 inputs and 8 outputs might
work. One more thing to consider would be that the total IO rate (data rate
- num ports) of a single CE has to be less than 2x the clock rate of the
CE-- this is because the CE shares the crossbar connection between all
ports, and the crossbar uses a 64 bit bus instead of 32 bits. For this
particular scenario, I might recommend an architecture like this...
Radio (high mclk) ==> single channel DDC (downsample by 32x or something)
==> Splitstream with 8 output ports ==> DDC with 8 input/output ports
For the DDC, there's a verilog parameter you can change that adds more
channels -- I believe it defaults to 2. You'll also want to change the NOC
ID of the updated DDC so you can create a new xml definition with 8 ports,
and then probably edit the gr-ettus block to provide 8 ports, too.
For the Splitstream, you may need to copy the existing block and create a
version that has 8 ports. I'm not sure off the top of my head but I think
it only provides 2 outputs.
Alternatively, you could investigate the rfnoc polyphase channelizer :) I
saw some activity back in February but not sure about current status.
Hope this helps,
EJ
On Thu, Apr 26, 2018, 4:00 AM Carlos Alberto Ruiz Naranjo via USRP-users <
usrp-users@lists.ettus.com> wrote:
I have seen that application will only allow a number of 10 custom blocks
on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing tests
with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hello,
thank you Derek and Ej. I am already beginning to understand what my
limitations are going to be.
I want channalizer in 8+8 variables and not evenly spaced channels. Then I
think that I cant use the rfnoc polyphase filter. The channels will be
processed independently on my computer.
This is my ideal scenario:
If I use a single DDC for radio channel (1:8) my IO rate is 100Mhz +
8x600Khz = 104.8Mhz, right? Then I need a CE clock rate > 209.6Mhz? Would
it be possible?
Thank you.
2018-04-26 12:26 GMT+02:00 EJ Kreinar ejkreinar@gmail.com:
Hi Carlos,
Unfortunately no -- that's not possible :)
A few reasons:
- As you've mentioned, there's an RFNoC CE limit... The generator refuses
to insert more than 10, but fundamentally I believe it's 16 total CEs
possible, so you get 14-15 usable CE spots depending on how many radio
blocks are instantiated. So you cannot actually create an FPGA image that
has the required blocks - I believe the sample rate on the RFNoC radio for X310 cannot be set to
32 kHz... the master_clock_rate has only a few predetermined values, so
you'll need to set the rate on the RFNoC: Radio to one of those clock rates
(otherwise it will coerce it for you).
The follow up suggestion of one DDC with 8 inputs and 8 outputs might
work. One more thing to consider would be that the total IO rate (data rate
- num ports) of a single CE has to be less than 2x the clock rate of the
CE-- this is because the CE shares the crossbar connection between all
ports, and the crossbar uses a 64 bit bus instead of 32 bits. For this
particular scenario, I might recommend an architecture like this...
Radio (high mclk) ==> single channel DDC (downsample by 32x or something)
==> Splitstream with 8 output ports ==> DDC with 8 input/output ports
For the DDC, there's a verilog parameter you can change that adds more
channels -- I believe it defaults to 2. You'll also want to change the NOC
ID of the updated DDC so you can create a new xml definition with 8 ports,
and then probably edit the gr-ettus block to provide 8 ports, too.
For the Splitstream, you may need to copy the existing block and create a
version that has 8 ports. I'm not sure off the top of my head but I think
it only provides 2 outputs.
Alternatively, you could investigate the rfnoc polyphase channelizer :) I
saw some activity back in February but not sure about current status.
Hope this helps,
EJ
On Thu, Apr 26, 2018, 4:00 AM Carlos Alberto Ruiz Naranjo via USRP-users <
usrp-users@lists.ettus.com> wrote:
I have seen that application will only allow a number of 10 custom blocks
on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing tests
with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Sorry, I have not attached the image:
2018-04-26 17:16 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello,
thank you Derek and Ej. I am already beginning to understand what my
limitations are going to be.
I want channalizer in 8+8 variables and not evenly spaced channels. Then I
think that I cant use the rfnoc polyphase filter. The channels will be
processed independently on my computer.
This is my ideal scenario:
If I use a single DDC for radio channel (1:8) my IO rate is 100Mhz +
8x600Khz = 104.8Mhz, right? Then I need a CE clock rate > 209.6Mhz? Would
it be possible?
Thank you.
2018-04-26 12:26 GMT+02:00 EJ Kreinar ejkreinar@gmail.com:
Hi Carlos,
Unfortunately no -- that's not possible :)
A few reasons:
- As you've mentioned, there's an RFNoC CE limit... The generator
refuses to insert more than 10, but fundamentally I believe it's 16 total
CEs possible, so you get 14-15 usable CE spots depending on how many radio
blocks are instantiated. So you cannot actually create an FPGA image that
has the required blocks - I believe the sample rate on the RFNoC radio for X310 cannot be set to
32 kHz... the master_clock_rate has only a few predetermined values, so
you'll need to set the rate on the RFNoC: Radio to one of those clock rates
(otherwise it will coerce it for you).
The follow up suggestion of one DDC with 8 inputs and 8 outputs might
work. One more thing to consider would be that the total IO rate (data rate
- num ports) of a single CE has to be less than 2x the clock rate of the
CE-- this is because the CE shares the crossbar connection between all
ports, and the crossbar uses a 64 bit bus instead of 32 bits. For this
particular scenario, I might recommend an architecture like this...
Radio (high mclk) ==> single channel DDC (downsample by 32x or something)
==> Splitstream with 8 output ports ==> DDC with 8 input/output ports
For the DDC, there's a verilog parameter you can change that adds more
channels -- I believe it defaults to 2. You'll also want to change the NOC
ID of the updated DDC so you can create a new xml definition with 8 ports,
and then probably edit the gr-ettus block to provide 8 ports, too.
For the Splitstream, you may need to copy the existing block and create a
version that has 8 ports. I'm not sure off the top of my head but I think
it only provides 2 outputs.
Alternatively, you could investigate the rfnoc polyphase channelizer :) I
saw some activity back in February but not sure about current status.
Hope this helps,
EJ
On Thu, Apr 26, 2018, 4:00 AM Carlos Alberto Ruiz Naranjo via USRP-users <
usrp-users@lists.ettus.com> wrote:
I have seen that application will only allow a number of 10 custom
blocks on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing
tests with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hi Carlos,
That's a non integer decimation rate as one problem. Hopefully the 600kHz
is slightly flexible? An even decimation rate will give you better
performance than an odd one, so what about 781.25 kHz? It's a nice
decimation of 128 from 100 MHz, you could cascade halfband filters. It also
means that 600 kHz is 76% of the sample bandwidth, the filter roll off
won't even come close to touching your main passband, but maybe you've
already factored in a margin. Getting rid of the CIC filter and doing some
careful sizing of the decimation filters will help reduce the resource
pressure.
Are you using TwinRXs? If not you will need to have an extra decimate by
two stage just at the output of the radio block since all other radios
output 200 MS/s.
You have purple and black lines in your figures, what do they indicate? Is
this a pure receive system?
Derek
On Thu, Apr 26, 2018 at 4:16 PM, Carlos Alberto Ruiz Naranjo via USRP-users
usrp-users@lists.ettus.com wrote:
Hello,
thank you Derek and Ej. I am already beginning to understand what my
limitations are going to be.
I want channalizer in 8+8 variables and not evenly spaced channels. Then I
think that I cant use the rfnoc polyphase filter. The channels will be
processed independently on my computer.
This is my ideal scenario:
If I use a single DDC for radio channel (1:8) my IO rate is 100Mhz +
8x600Khz = 104.8Mhz, right? Then I need a CE clock rate > 209.6Mhz? Would
it be possible?
Thank you.
2018-04-26 12:26 GMT+02:00 EJ Kreinar ejkreinar@gmail.com:
Hi Carlos,
Unfortunately no -- that's not possible :)
A few reasons:
- As you've mentioned, there's an RFNoC CE limit... The generator
refuses to insert more than 10, but fundamentally I believe it's 16 total
CEs possible, so you get 14-15 usable CE spots depending on how many radio
blocks are instantiated. So you cannot actually create an FPGA image that
has the required blocks - I believe the sample rate on the RFNoC radio for X310 cannot be set to
32 kHz... the master_clock_rate has only a few predetermined values, so
you'll need to set the rate on the RFNoC: Radio to one of those clock rates
(otherwise it will coerce it for you).
The follow up suggestion of one DDC with 8 inputs and 8 outputs might
work. One more thing to consider would be that the total IO rate (data rate
- num ports) of a single CE has to be less than 2x the clock rate of the
CE-- this is because the CE shares the crossbar connection between all
ports, and the crossbar uses a 64 bit bus instead of 32 bits. For this
particular scenario, I might recommend an architecture like this...
Radio (high mclk) ==> single channel DDC (downsample by 32x or something)
==> Splitstream with 8 output ports ==> DDC with 8 input/output ports
For the DDC, there's a verilog parameter you can change that adds more
channels -- I believe it defaults to 2. You'll also want to change the NOC
ID of the updated DDC so you can create a new xml definition with 8 ports,
and then probably edit the gr-ettus block to provide 8 ports, too.
For the Splitstream, you may need to copy the existing block and create a
version that has 8 ports. I'm not sure off the top of my head but I think
it only provides 2 outputs.
Alternatively, you could investigate the rfnoc polyphase channelizer :) I
saw some activity back in February but not sure about current status.
Hope this helps,
EJ
On Thu, Apr 26, 2018, 4:00 AM Carlos Alberto Ruiz Naranjo via USRP-users <
usrp-users@lists.ettus.com> wrote:
I have seen that application will only allow a number of 10 custom
blocks on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing
tests with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Good! I have no problem with developing a block, Dario. :)
I have to consult it, but I do not think there's a problem with 781.25 Khz.
Yes, I use TwinRXs. Purple lines are FPGA to PC data flow. Yes, it is a
pure receive system.
Thank you :)
2018-04-26 17:43 GMT+02:00 Derek Kozel derek.kozel@ettus.com:
Hi Carlos,
That's a non integer decimation rate as one problem. Hopefully the 600kHz
is slightly flexible? An even decimation rate will give you better
performance than an odd one, so what about 781.25 kHz? It's a nice
decimation of 128 from 100 MHz, you could cascade halfband filters. It also
means that 600 kHz is 76% of the sample bandwidth, the filter roll off
won't even come close to touching your main passband, but maybe you've
already factored in a margin. Getting rid of the CIC filter and doing some
careful sizing of the decimation filters will help reduce the resource
pressure.
Are you using TwinRXs? If not you will need to have an extra decimate by
two stage just at the output of the radio block since all other radios
output 200 MS/s.
You have purple and black lines in your figures, what do they indicate? Is
this a pure receive system?
Derek
On Thu, Apr 26, 2018 at 4:16 PM, Carlos Alberto Ruiz Naranjo via
USRP-users usrp-users@lists.ettus.com wrote:
Hello,
thank you Derek and Ej. I am already beginning to understand what my
limitations are going to be.
I want channalizer in 8+8 variables and not evenly spaced channels. Then I
think that I cant use the rfnoc polyphase filter. The channels will be
processed independently on my computer.
This is my ideal scenario:
If I use a single DDC for radio channel (1:8) my IO rate is 100Mhz +
8x600Khz = 104.8Mhz, right? Then I need a CE clock rate > 209.6Mhz? Would
it be possible?
Thank you.
2018-04-26 12:26 GMT+02:00 EJ Kreinar ejkreinar@gmail.com:
Hi Carlos,
Unfortunately no -- that's not possible :)
A few reasons:
- As you've mentioned, there's an RFNoC CE limit... The generator
refuses to insert more than 10, but fundamentally I believe it's 16 total
CEs possible, so you get 14-15 usable CE spots depending on how many radio
blocks are instantiated. So you cannot actually create an FPGA image that
has the required blocks - I believe the sample rate on the RFNoC radio for X310 cannot be set
to 32 kHz... the master_clock_rate has only a few predetermined values, so
you'll need to set the rate on the RFNoC: Radio to one of those clock rates
(otherwise it will coerce it for you).
The follow up suggestion of one DDC with 8 inputs and 8 outputs might
work. One more thing to consider would be that the total IO rate (data rate
- num ports) of a single CE has to be less than 2x the clock rate of the
CE-- this is because the CE shares the crossbar connection between all
ports, and the crossbar uses a 64 bit bus instead of 32 bits. For this
particular scenario, I might recommend an architecture like this...
Radio (high mclk) ==> single channel DDC (downsample by 32x or
something) ==> Splitstream with 8 output ports ==> DDC with 8 input/output
ports
For the DDC, there's a verilog parameter you can change that adds more
channels -- I believe it defaults to 2. You'll also want to change the NOC
ID of the updated DDC so you can create a new xml definition with 8 ports,
and then probably edit the gr-ettus block to provide 8 ports, too.
For the Splitstream, you may need to copy the existing block and create
a version that has 8 ports. I'm not sure off the top of my head but I think
it only provides 2 outputs.
Alternatively, you could investigate the rfnoc polyphase channelizer :)
I saw some activity back in February but not sure about current status.
Hope this helps,
EJ
On Thu, Apr 26, 2018, 4:00 AM Carlos Alberto Ruiz Naranjo via USRP-users
usrp-users@lists.ettus.com wrote:
I have seen that application will only allow a number of 10 custom
blocks on the X3xx series.
Would it be a good idea to create a DDC block with 8 inputs and 8
independent outputs? Or can I have problems with the timing constraints
?
2018-04-25 14:43 GMT+02:00 Carlos Alberto Ruiz Naranjo <
carlosruiznaranjo@gmail.com>:
Hello!
I will receive my new USRP X310 in the coming weeks and I'm doing
tests with the RFNoc environment.
I'm trying to set up an example of my project and I have some doubts. I
want to process a channel in 8 DDCs:
But I have a problem to split the channel. I have thought in:
It's possible?
Thank you.
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
