Hi everyone, I follow the instruction in the following website in order to add new IP to my X310. http://www.synchronouslabs.com/blog/creating-a-custom-rfnoc-block-with-using-xillinx-ip At the last stage in the website, in order to build the bin file that burn to the FPGA, they use the make.py script. I try to find this script, but I didn't success ,so I try to build the bin with the uhd_usrp_builder.py code. The problem is, that the IP that I add to the Makefile like in the website, don't really add like all the others IP, that define by default. The error that I get is : module fir_compiler_0 don't found. When I look on the build.log I saw that my IP don't add to the project. Can someone help me how to download the make.py file or how to finish the process with the uhd_usrp_builder.py script. Thank in advance, Ishai The information in this e-mail transmission contains proprietary and business sensitive information. Unauthorized interception of this e-mail may constitute a violation of law. If you are not the intended recipient, you are hereby notified that any review, dissemination, distribution or duplication of this communication is strictly prohibited. You are also asked to contact the sender by reply email and immediately destroy all copies of the original message.

Hello Allouche, the "make.py" script was renamed to be the uhd_image_builder.py [1], which I assume is the one you are referring to when you mention the "uhd_usrp_builder.py". The fact that your IP is not being correctly picked up might be related to your makefiles, which you'd have to review carefully. Have a look at this example [2] and compare it with your implementation. Cheers, - Nicolas [1] https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/tools/scripts/uhd_image_builder.py [2] https://github.com/ejk43/rfnoc-ootexample On Sun, May 13, 2018 at 1:14 PM, Allouche Ishai via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi everyone, > > > > I follow the instruction in the following website in order to add new IP > to my X310. http://www.synchronouslabs.com/blog/creating-a-custom- > rfnoc-block-with-using-xillinx-ip > > > > At the last stage in the website, in order to build the bin file that burn > to the FPGA, they use the make.py script. > > I try to find this script, but I didn’t success ,so I try to build the bin > with the uhd_usrp_builder.py code. > > The problem is, that the IP that I add to the Makefile like in the > website, don’t really add like all the others IP, that define by default. > > The error that I get is : module fir_compiler_0 don’t found. When I look > on the build.log I saw that my IP don’t add to the project. > > > > Can someone help me how to download the make.py file or how to finish the > process with the uhd_usrp_builder.py script. > > > > Thank in advance, > > Ishai > > > *The information in this electronic message and any attachments (the > "Message") is intended for one or more specific individuals or entities, > and may contain proprietary, business sensitive, confidential or otherwise > protected by law information. Unauthorized interception of this e-mail may > constitute a violation of law. If you are not the intended recipient, > please notify the sender immediately, delete this Message, and do not > disclose, distribute, or copy it to any third party or otherwise use this > Message. Electronic messages are not secure or error free and can contain > viruses or may be delayed, and the sender is not liable for any of these > occurrences. This Message is not intended to create, and receipt of it does > not constitute, a contractual or other binding relationship.* > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >