How far can I push a crystal?
About $4 on epay will get you a DDS knurdle with crystal reference
that'll deliver...
Rick Karlquist
Ed Breya wrote:
Maybe I should clarify what I meant by pushing the crystal frequency.
I
meant only using various topologies and electronic components in the
associated circuitry, that would detune it from its natural resonance
far enough to reach the new frequency, and still have it be sort of a
narrow-bandwidth crystal oscillator - not doing any mechanical changes
to the crystal element itself.
Since the ceramic resonators seem to work well, and can be pushed (or
pulled?) fairly far away by proper selection of the associated
component
values, I was wondering how far quartz crystals can reasonably go. I
Since you asked:
You can get something like a range of 0.1% by resonating out the
holder capacitance with a shunt inductor. You then put this
assembly in series with an inductor and varactor. If you want to
get into the lunatic fringe, you use a high Q inductor wound on
Fair-Rite 61 or 67. Now you can seriously pull the crystal below
its resonant frequency. How far you can go depends on the Q of
the inductor. I am not sure if you can also pull it above,
but even if you could, there are spurious resonances up there that
could get you. The lunatic fringe might get you .2 or .3%, still
not .6%. You'll definitely take a hit in temperature stability
and phase noise with high pulling. If you don't have experience
with VCXO's, you will find the circuit design quite challenging.
It wasn't clear if you needed a 10.05944 MHz VCXO, or just a
source at that frequency. There a lots of one chip synthesizers
that could generate that frequency as I'm sure you know.
Rick Karlquist N6RK
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Bob, please tell me more about cascading the DFFs. I was only using one
half of the '74, with the other inactive, so both are available for the
task. From your description it sounds like I just run the Q from the
first DFF to the D of the second, clock them together from the 1 or 10
MHz, and take the cleaned up difference signal from the Q of the second.
So, I think what it means is that the same information should pass
through, just delayed by one sampling clock cycle, and scrubbed of any
edge uncertainty of an analog nature, that would otherwise be passed to
the phase detector. Right? I would definitely do this if no additional
logic packages are required.
If a single-PLL type we discussed earlier is workable, I won't even need
to worry about the second PLL system. It all depends on whether the
phase detector frequency will be high enough. I'll be thinking through
that and trying a few experiments. It's simple enough that I could even
just build it and see what happens. If it's not right, then I'll just go
with the previous plan, with high confidence - and a two-stage sampler.
Regarding the oscillators - yes, having different signals present in
common packages is what got me into this trouble in the first place. As
I mentioned earlier, I had optimized the original design for compactness
and minimum package count, so I had every signal in the box going every
which way, all mixed up. I had used a different method for making the
10.7 MHz though - building it up by mixing various divided frequencies,
then filtering it with cascaded 10.7 MHz IF filters. Most of the stuff
went right around the filters anyway, since there was so much whizzing
around in there.
In case anyone is wondering why I'm so hung up on this 10.7 MHz thing:
For this particular tracking generator project, I just need to
synthesize one fixed, "correct" reference frequency with the simplest,
most compact scheme that performs well enough. The original design
evolved from using the 10.7 MHz base frequency, but it isn't actually
needed per se. If anyone comes up with sets of numbers that seem to work
in a single-PLL scheme, and fit the constraints evident in this
discussion, please let me know.
I have other tracking generator projects in the works though, that will
cover most or all of the 8566B span of ~0 to 24 GHz, and need to produce
various numeric and harmonic relationships for IFs and frequency control
- all of these can be readily integer-derived from the fundamental 10
and 10.7 MHz references. In all cases, the ultimate reference is the 10
MHz used or produced by the 8566B, so everything is phase locked.
Ed
On 18.01.2013 22:41, shalimr9@gmail.com wrote:
10.059 used to be a standard frequency for some 8051 microcontrollers. Should not be too hard to find.
No, it was 11.0592
Regards,
Javier
HI
Different Bob, but here's the flip flop answer....
On Jan 18, 2013, at 5:11 PM, Ed Breya eb@telight.com wrote:
Bob, please tell me more about cascading the DFFs. I was only using one half of the '74, with the other inactive, so both are available for the task. From your description it sounds like I just run the Q from the first DFF to the D of the second, clock them together from the 1 or 10 MHz, and take the cleaned up difference signal from the Q of the second. So, I think what it means is that the same information should pass through, just delayed by one sampling clock cycle, and scrubbed of any edge uncertainty of an analog nature, that would otherwise be passed to the phase detector. Right? I would definitely do this if no additional logic packages are required.
The gotcha with any flip flop is that it can get confused if you hit it just wrong. Exactly what constitutes wrong varies a bit depending on what kind of flip flop it is. In the case of a D flip flop with an edge sensitive clock, wrong is the data and clock changing at just about the same time. There is a possibility that the flip flop goes into oscillation rather than latching to either a 1 or a 0 state. If there's enough gain, it can keep on going until the next clock edge comes along. Obviously, this isn't what you want it to do. By cascading flip flops, you have much less chance of things hitting the final flip flop and creating an oscillator.
Bob
If a single-PLL type we discussed earlier is workable, I won't even need to worry about the second PLL system. It all depends on whether the phase detector frequency will be high enough. I'll be thinking through that and trying a few experiments. It's simple enough that I could even just build it and see what happens. If it's not right, then I'll just go with the previous plan, with high confidence - and a two-stage sampler.
Regarding the oscillators - yes, having different signals present in common packages is what got me into this trouble in the first place. As I mentioned earlier, I had optimized the original design for compactness and minimum package count, so I had every signal in the box going every which way, all mixed up. I had used a different method for making the 10.7 MHz though - building it up by mixing various divided frequencies, then filtering it with cascaded 10.7 MHz IF filters. Most of the stuff went right around the filters anyway, since there was so much whizzing around in there.
In case anyone is wondering why I'm so hung up on this 10.7 MHz thing: For this particular tracking generator project, I just need to synthesize one fixed, "correct" reference frequency with the simplest, most compact scheme that performs well enough. The original design evolved from using the 10.7 MHz base frequency, but it isn't actually needed per se. If anyone comes up with sets of numbers that seem to work in a single-PLL scheme, and fit the constraints evident in this discussion, please let me know.
I have other tracking generator projects in the works though, that will cover most or all of the 8566B span of ~0 to 24 GHz, and need to produce various numeric and harmonic relationships for IFs and frequency control - all of these can be readily integer-derived from the fundamental 10 and 10.7 MHz references. In all cases, the ultimate reference is the 10 MHz used or produced by the 8566B, so everything is phase locked.
Ed
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Ed, busy weekend happening, delayed my response. Bob Camp's reply regarding the
DFF was spot on, and your connections below are just what to do. When feeding a
DFF with non-synchronous signals it's likely setup and hold times will be
violated. When that happens oscillation is possible, but usually dies out fairly
quickly so that setup and hold times are met for the second DFF. The second DFF
is thus much less likely to exhibit an incorrect output condition.
I'm not sure about a single-PLL approach, thinking of multiplications of 953 and
38 as two steps, and thus two PLLs. If you can multiply by 36214 (to
1207.133MHz) in a single step I'd like to know more about your approach. In
general I feel uncomfortable with such a high multiplication factor, just
because of the time lag through the long divider. Since I'm no PLL expert I may
be totally wrong, so any comments made by you or others will improve my
knowledge base.
I had forgotten your earlier email about the previous noisy attempt, sorry my
oscillator comment was redundant. And thanks for the background on the 10.7MHz
starting point. Regarding coming up with a set of numbers for a single PLL
approach I find a spreadsheet and the two online calculators (decimal to
fraction, and factoring) make for easier work. But it will be up to you to
decide what scheme best fits your needs. Good luck with the project!
Bob L.
----- Original Message ----
From: Ed Breya eb@telight.com
To: time-nuts@febo.com
Sent: Fri, January 18, 2013 5:13:00 PM
Subject: Re: [time-nuts] How far can I push a crystal?
Bob, please tell me more about cascading the DFFs. I was only using one half of
the '74, with the other inactive, so both are available for the task. From your
description it sounds like I just run the Q from the first DFF to the D of the
second, clock them together from the 1 or 10 MHz, and take the cleaned up
difference signal from the Q of the second. So, I think what it means is that
the same information should pass through, just delayed by one sampling clock
cycle, and scrubbed of any edge uncertainty of an analog nature, that would
otherwise be passed to the phase detector. Right? I would definitely do this if
no additional logic packages are required.
If a single-PLL type we discussed earlier is workable, I won't even need to
worry about the second PLL system. It all depends on whether the phase detector
frequency will be high enough. I'll be thinking through that and trying a few
experiments. It's simple enough that I could even just build it and see what
happens. If it's not right, then I'll just go with the previous plan, with high
confidence - and a two-stage sampler.
Regarding the oscillators - yes, having different signals present in common
packages is what got me into this trouble in the first place. As I mentioned
earlier, I had optimized the original design for compactness and minimum
package count, so I had every signal in the box going every which way, all
mixed up. I had used a different method for making the 10.7 MHz though -
building it up by mixing various divided frequencies, then filtering it with
cascaded 10.7 MHz IF filters. Most of the stuff went right around the filters
anyway, since there was so much whizzing around in there.
In case anyone is wondering why I'm so hung up on this 10.7 MHz thing: For
this particular tracking generator project, I just need to synthesize one
fixed, "correct" reference frequency with the simplest, most compact scheme
that performs well enough. The original design evolved from using the 10.7 MHz
base frequency, but it isn't actually needed per se. If anyone comes up with
sets of numbers that seem to work in a single-PLL scheme, and fit the
constraints evident in this discussion, please let me know.
I have other tracking generator projects in the works though, that will cover
most or all of the 8566B span of ~0 to 24 GHz, and need to produce various
numeric and harmonic relationships for IFs and frequency control - all of these
can be readily integer-derived from the fundamental 10 and 10.7 MHz references.
In all cases, the ultimate reference is the 10 MHz used or produced by the
8566B, so everything is phase locked.
Ed
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I tried to send this message on Sunday, but for some reason it didn't go
through, so here it is again. Please excuse any redundancy if the
original shows up. I will have an update of the project soon.
Hi Bob L.,
Your suggestion of the 300/953 scheme was inspiration for what hopefully
will be the simplest solution of all - I've started building it. First,
I should clarify more, that the original scheme actually has three
phase-locked loops - a 10.7 MHz, a 10.05944444 MHz, and the final one,
1207.1333333 MHz. The last one is a PLO brick that just multiplies any
RF input by any n within reason to phase lock the microwave output (to
nth harmonic of input). I wasn't counting that one, since it's more or
less a fixed function, but it's a variable (arbitrary n) in the numbers
game. So, when I was referring to getting rid of one PLL, I meant not
needing to produce the intermediate 10.7 MHz, since the "953" gives a
rational number solution directly from 1 or 10 MHz - this is the "single
PLL" scenario.
I tested the PLO and microwave section with 15.883333333 MHz = (10
MHz/600)*953 from a synthesizer, and it worked just fine. The PLO is
tuned near 1207 MHz, and uses whatever n lands it within lock range, so
n=76 in this case. If you adjust the cavity, n can just as easily be 75
or 77, with different output frequencies, or a number of numbers that
satisfy the bounds of operation. So, the trick is to produce that one
"correct" frequency from the 10 MHz reference, cleanly enough to get the
job done, and feed it to the PLO - the n value takes care of itself.
The way it's partitioned now, I will have one can containing the
15.8833333 MHz VCXO (74HC86 and a 16 MHz ceramic resonator), two LAN
LPFs, a 74HC4020 feedback divider (1/953), and a CD4046B PLL. A second
can, which is needed anyway for handling the various external and
internal 10 and 1 MHz references, will not only route and scale, but
will also include the divider to make the 16.66666 kHz (10 MHz/600)
reference for the other box.
So, the overall synthesis chain is (10 MHz/600)95376=1207.133333 MHz.
Pretty simple.
Ed
Hi Ed,
Thanks, your explanation of single PLL helps. I see it now somewhat in the sense
of "only have to BUILD a single PLL" to make things work. I can appreciate the
simplified effort greatly. I also now think of the PLO as an oscillator locked
to a tuned harmonic that (probably) comes from some sort of comb generator, so
that's not a PLL in the more conventional sense, and the resulting system
becomes a true "single PLL" design. I'll look forward to hearing how it works
out.
Bob L.
----- Original Message ----
From: Ed Breya eb@telight.com
To: time-nuts@febo.com
Sent: Tue, January 22, 2013 11:46:35 PM
Subject: Re: [time-nuts] How far can I push a crystal?
I tried to send this message on Sunday, but for some reason it didn't go
through, so here it is again. Please excuse any redundancy if the original shows
up. I will have an update of the project soon.
Hi Bob L.,
Your suggestion of the 300/953 scheme was inspiration for what hopefully will
be the simplest solution of all - I've started building it. First, I should
clarify more, that the original scheme actually has three phase-locked loops -
a 10.7 MHz, a 10.05944444 MHz, and the final one, 1207.1333333 MHz. The last
one is a PLO brick that just multiplies any RF input by any n within reason to
phase lock the microwave output (to nth harmonic of input). I wasn't counting
that one, since it's more or less a fixed function, but it's a variable
(arbitrary n) in the numbers game. So, when I was referring to getting rid of
one PLL, I meant not needing to produce the intermediate 10.7 MHz, since the
"953" gives a rational number solution directly from 1 or 10 MHz - this is the
"single PLL" scenario.
I tested the PLO and microwave section with 15.883333333 MHz = (10
MHz/600)*953 from a synthesizer, and it worked just fine. The PLO is tuned near
1207 MHz, and uses whatever n lands it within lock range, so n=76 in this case.
If you adjust the cavity, n can just as easily be 75 or 77, with different
output frequencies, or a number of numbers that satisfy the bounds of operation.
So, the trick is to produce that one "correct" frequency from the 10 MHz
reference, cleanly enough to get the job done, and feed it to the PLO - the n
value takes care of itself.
The way it's partitioned now, I will have one can containing the 15.8833333
MHz VCXO (74HC86 and a 16 MHz ceramic resonator), two LAN LPFs, a 74HC4020
feedback divider (1/953), and a CD4046B PLL. A second can, which is needed
anyway for handling the various external and internal 10 and 1 MHz references,
will not only route and scale, but will also include the divider to make the
16.66666 kHz (10 MHz/600) reference for the other box.
So, the overall synthesis chain is (10 MHz/600)95376=1207.133333 MHz. Pretty
simple.
Ed
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