Can someone shed some light on this comment: https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/b200/b200_io.v#L345 // In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's. This looks to be exactly what I want - the digitized data from subdevice A on a B210 sent to both DDCs, which can then be DSP tuned independently and two separate parts of the digitized data transferred to the host. Can this be done without modifying the UHD driver or the FPGA image? Thanks, Jacob

// In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's.

Jacob, I have no recollection of enhancing UHD to support this functionality at the time I wrote this RTL…which is not to say that some else hasn't since done so…I haven't been following closely. But as you correctly deduced, the raw capability to have two independent DDC's driven by a single Rx sample stream from the RFIC is baked into the standard FPGA. As a side note: There is a pretty easy trick to have two active DDC's in B200 with UHD thinking it's in single channel mode, though it has some constraints…both DDC's need to have the same decimation ratio, and the NCO's have equal but opposite frequencies so that they symmetrically straddle DC from the RFIC. The 2 sample streams are returned interleaved {i0,q0}, {i1,q1},{i0,q0}…etc are you just demux them downstream of UHD. UHD is completely obvious to the fact that the B200 returns twice the bit rate that it programmed. The NCO's are both programmed by the same register and H/W just inverts the frequency to the second one. Clearly this is a custom FPGA image, but its a fairly easy project, the only new logic is the interleaver at the out put of the 2 DDC's. I have this code, but haven't published it. I could be persuaded to, but it will come without any support. -ian On Jan 18, 2017, at 9:30 PM, Jacob Gilbert via USRP-users <usrp-users@lists.ettus.com> wrote: > Can someone shed some light on this comment: https://github.com/EttusResearch/fpga/blob/maint/usrp3/top/b200/b200_io.v#L345 > > // In SISO mode data is replicated onto both CH0 and CH1 for max flexibility in using the DDC's. > > This looks to be exactly what I want - the digitized data from subdevice A on a B210 sent to both DDCs, which can then be DSP tuned independently and two separate parts of the digitized data transferred to the host. > > Can this be done without modifying the UHD driver or the FPGA image? > > Thanks, > Jacob > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Ian, Thanks for the information. I'm a little concerned that the approach you outlined will cause issues with timing, have you seen that to be the case? My application requires accuracy to 10's of µs. I modified UHD to force the board into SISO mode (by commenting this line out https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/b200/b200_impl.cpp#L1156) which 'works', however it looks like I am getting twice the sample rate I request, and if the sample rate is equal to the master clock rate I get spectrum repetition (see attachment). I was not expecting this, can the DDC block interpolate? If you had any insights into what is going on here please let me know. I also need at least 40 MS/s into the CORDICs (so I will need to be running the 9361 in SISO mode), and one TX channel so there will need to be some logic to get past the logic protecting the limitations of the AD9361 w/r/t sample rate and channel combinations. Any thoughts appreciated before I get too far into the weeds with this. Thanks, Jacob On Wed, Jan 18, 2017 at 11:42 PM, Ian Buckley <ianb@ionconcepts.com> wrote: > Jacob, > I have no recollection of enhancing UHD to support this functionality at > the time I wrote this RTL…which is not to say that some else hasn't since > done so…I haven't been following closely. > But as you correctly deduced, the raw capability to have two independent > DDC's driven by a single Rx sample stream from the RFIC is baked into the > standard FPGA. > > As a side note: There is a pretty easy trick to have two active DDC's in > B200 with UHD thinking it's in single channel mode, though it has some > constraints…both DDC's need to have the same decimation ratio, and the > NCO's have equal but opposite frequencies so that they symmetrically > straddle DC from the RFIC. The 2 sample streams are returned interleaved > {i0,q0}, {i1,q1},{i0,q0}…etc are you just demux them downstream of UHD. > UHD is completely obvious to the fact that the B200 returns twice the bit > rate that it programmed. The NCO's are both programmed by the same register > and H/W just inverts the frequency to the second one. Clearly this is a > custom FPGA image, but its a fairly easy project, the only new logic is the > interleaver at the out put of the 2 DDC's. > > I have this code, but haven't published it. I could be persuaded to, but > it will come without any support. > -ian > > > On Jan 18, 2017, at 9:30 PM, Jacob Gilbert via USRP-users < > usrp-users@lists.ettus.com> wrote: > > Can someone shed some light on this comment: https://github.com/ > EttusResearch/fpga/blob/maint/usrp3/top/b200/b200_io.v#L345 > > // In SISO mode data is replicated onto both CH0 and CH1 for max > flexibility in using the DDC's. > > This looks to be exactly what I want - the digitized data from subdevice A > on a B210 sent to both DDCs, which can then be DSP tuned independently and > two separate parts of the digitized data transferred to the host. > > Can this be done without modifying the UHD driver or the FPGA image? > > Thanks, > Jacob > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > >

 // NCO

Jacob, The line you changed in UHD will only force the IO interface on the FPGA to operate in SISO mode, the RFIC will continue to operate as SISO or MIMO as programmed. If the RFIC is in MIMO mode with your change in place then "interesting(tm)" things will happen because the IQ data for both channels will not be de-interleaved and fed as a single sample stream to the DDC....perhaps thats what you have in your spectrum? You should not beed to make any UHD changes for what I suggested, it's all FPGA trickery. 1) You edit radio_b200.v to add a second instance of a DDC to the Channel 0 radio like so. Both these DDC's alias in the address map and receive identical programming: + > + ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24)) ddc_chain_upper > + (.clk(radio_clk), .rst(radio_rst), .clr(1'b0), > + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), > + .rx_fe_i({rx[31:16],8'd0}),.rx_fe_q({rx[15:0],8'd0}), > + .sample(sample_rx_upper), .run(run_rx), .strobe(strobe_rx_upper), > + .debug() ); > + > + ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24), > .NEGATE_OFFSET(1)) ddc_chain_lower > + (.clk(radio_clk), .rst(radio_rst), .clr(1'b0), > + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), > + .rx_fe_i({rx[31:16],8'd0}),.rx_fe_q({rx[15:0],8'd0}), > + .sample(sample_rx_lower), .run(run_rx), .strobe(strobe_rx_lower), > + .debug() ); > + > + // Delay output of ddc_chain_lower by one radio clock so it is offset > in time from ddc_chain_upper (with which it runs in lockstep) > + always @(posedge radio_clk) begin > + sample_rx_lower_reg <= sample_rx_lower; > + strobe_rx_lower_reg <= strobe_rx_lower; > + end > + > + // Priority mux of both DDC's. Upper always wins but they will only > colide if decimation is 1. > + assign strobe_rx = (strobe_rx_upper) ? strobe_rx_upper : > strobe_rx_lower_reg; > + assign sample_rx = (strobe_rx_upper) ? sample_rx_upper : > sample_rx_lower_reg; > + Since they work in lockstep and produce results in the same clock cycle you delay the results from the second DDC at the output by one clock cycle. This allows you to interleave the results with a simple MUX, but subjects you to the limitation that you must always configure the DDC to decimate by 2 or greater so that the output is not valid every clock cycle. The downstream packetization logic just counts samples in and is oblivious to this trickery. Each packet will still get tagged with correct time metadata that will give the same timing accuracy as a stock B200. 2) You modify the generic DDC slightly so that as a build time option it negates the programmed NCO frequency. diff --git a/usrp3/lib/dsp/ddc_chain.v b/usrp3/lib/dsp/ddc_chain.v > index f27bf09..fa00567 100644 > --- a/usrp3/lib/dsp/ddc_chain.v > +++ b/usrp3/lib/dsp/ddc_chain.v > @@ -11,7 +11,8 @@ module ddc_chain > parameter DSPNO = 0, > parameter WIDTH = 24, > parameter NEW_HB_DECIM = 0, > - parameter DEVICE = "SPARTAN6" > + parameter DEVICE = "SPARTAN6", > + parameter NEGATE_OFFSET = 0 > ) > (input clk, input rst, input clr, > input set_stb, input [7:0] set_addr, input [31:0] set_data, > @@ -82,13 +83,26 @@ module ddc_chain > end > > // NCO > - always @(posedge clk) > - if(rst) > - phase <= 0; > - else if(~run) > - phase <= 0; > - else > - phase <= phase + phase_inc; > + generate > + if (NEGATE_OFFSET == 1) begin: inverted > + always @(posedge clk) > + if(rst) > + phase <= 0; > + else if(~run) > + phase <= 0; > + else > + phase <= phase + ~(phase_inc) + 1'b1; > + end else begin : non_inverted > + always @(posedge clk) > + if(rst) > + phase <= 0; > + else if(~run) > + phase <= 0; > + else > + phase <= phase + phase_inc; > + end > + endgenerate > + 3) You program (via UHD/GR etc) the B200 as SISO with a master clock rate that is great enough that it encompasses the bandwidth span of your two channels plus their intervening separation, you set sample rate to be large enough to capture the band width of the larger of your 2 channels after channelization. You tune the B200 using a manual tuning policy that allows you to explicitly set the RF LO and DSP LO individually. The (rx) RF LO is set to the midpoint between the 2 channel centers, and the DSP LO is set to the distance from the RF LO to one channels center. You then de-interleave individual complex samples as the first step in you SDR application to get the 2 channels. 4) If the FPGA is overfull, then simply delete Radio1 (like a B200, look for the build time parameter) for this custom build. -Ian On Fri, Jan 20, 2017 at 7:40 AM, Jacob Gilbert <mrjacobagilbert@gmail.com> wrote: > Ian, > > Thanks for the information. I'm a little concerned that the approach you > outlined will cause issues with timing, have you seen that to be the case? > My application requires accuracy to 10's of µs. > > I modified UHD to force the board into SISO mode (by commenting this line > out https://github.com/EttusResearch/uhd/blob/master/ > host/lib/usrp/b200/b200_impl.cpp#L1156) which 'works', however it looks > like I am getting twice the sample rate I request, and if the sample rate > is equal to the master clock rate I get spectrum repetition (see > attachment). I was not expecting this, can the DDC block interpolate? If > you had any insights into what is going on here please let me know. > > I also need at least 40 MS/s into the CORDICs (so I will need to be > running the 9361 in SISO mode), and one TX channel so there will need to be > some logic to get past the logic protecting the limitations of the AD9361 > w/r/t sample rate and channel combinations. Any thoughts appreciated before > I get too far into the weeds with this. > > Thanks, > Jacob > > On Wed, Jan 18, 2017 at 11:42 PM, Ian Buckley <ianb@ionconcepts.com> > wrote: > >> Jacob, >> I have no recollection of enhancing UHD to support this functionality at >> the time I wrote this RTL…which is not to say that some else hasn't since >> done so…I haven't been following closely. >> But as you correctly deduced, the raw capability to have two independent >> DDC's driven by a single Rx sample stream from the RFIC is baked into the >> standard FPGA. >> >> As a side note: There is a pretty easy trick to have two active DDC's in >> B200 with UHD thinking it's in single channel mode, though it has some >> constraints…both DDC's need to have the same decimation ratio, and the >> NCO's have equal but opposite frequencies so that they symmetrically >> straddle DC from the RFIC. The 2 sample streams are returned interleaved >> {i0,q0}, {i1,q1},{i0,q0}…etc are you just demux them downstream of UHD. >> UHD is completely obvious to the fact that the B200 returns twice the bit >> rate that it programmed. The NCO's are both programmed by the same register >> and H/W just inverts the frequency to the second one. Clearly this is a >> custom FPGA image, but its a fairly easy project, the only new logic is the >> interleaver at the out put of the 2 DDC's. >> >> I have this code, but haven't published it. I could be persuaded to, but >> it will come without any support. >> -ian >> >> >> On Jan 18, 2017, at 9:30 PM, Jacob Gilbert via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >> Can someone shed some light on this comment: https://github.com/Et >> tusResearch/fpga/blob/maint/usrp3/top/b200/b200_io.v#L345 >> >> // In SISO mode data is replicated onto both CH0 and CH1 for max >> flexibility in using the DDC's. >> >> This looks to be exactly what I want - the digitized data from subdevice >> A on a B210 sent to both DDCs, which can then be DSP tuned independently >> and two separate parts of the digitized data transferred to the host. >> >> Can this be done without modifying the UHD driver or the FPGA image? >> >> Thanks, >> Jacob >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >> >