All, I am trying to offload some of my processing power onto my X310's FPGA. I have the environment set up but still find myself confused on how to build the out of tree block. I was able to add a block and I'm not sure what to do next? My design process is as follows: Matlab, get HDL code for DSP algorithms, and deploy it on the RFNOC? My goal is to start out with implementing an adaptive filter on the FPGA. When I looked in the FIR filter .v example I wasn't able to match how this code works with the rfnoc environment. When I add my new oot block I have the verilog code similar to the gain block example but not sure what else needs to be changed besides dropping in the verilog code into the newly_added_oot_block.v Is there any more documentation I can follow to make sure I am following the right path? Any pointers would be appreciated! Best regards

On Sat, Feb 10, 2024 at 2:47 PM Chris <gaytanc4@gmail.com> wrote: > All, I am trying to offload some of my processing power onto my X310's > FPGA. I have the environment set up but still find myself confused on how > to build the out of tree block. I was able to add a block and I'm not sure > what to do next? > > > My design process is as follows: Matlab, get HDL code for DSP algorithms, > and deploy it on the RFNOC? > > My goal is to start out with implementing an adaptive filter on the FPGA. > When I looked in the FIR filter .v example I wasn't able to match how this > code works with the rfnoc environment. When I add my new oot block I have > the verilog code similar to the gain block example but not sure what else > needs to be changed besides dropping in the verilog code into the > newly_added_oot_block.v > > Is there any more documentation I can follow to make sure I am following > the right path? > Using the rfnoc_image_builder tool isn't the most straightforward thing to do, but it is a decent path. First, I typically set things up in my environment as follows: export UHD_FPGA_DIR=/path/to/uhd/fpga export VIVADO_PATH=/path/to/Vivado export RFNOC_OOT=/path/to/oot In the OOT directory, there are a few directories: - blocks: The yml definitions of your custom blocks - icores: The yml definitions of your entire RFNoC image, similar to the default Ettus core: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x300/x310_rfnoc_image_core.yml - fpga: The FPGA source for each of the RFNoC blocks In the fpga directory, I have a Makefile.srcs which simply looks like: RFNOC_FPGA_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) include $(RFNOC_FPGA_DIR)/rfnoc_block_first/Makefile.srcs include $(RFNOC_FPGA_DIR)/rfnoc_block_second/Makefile.srcs So the above has two blocks that want to be included with the possibility to build. In each of my block directories, where the actual code lives, there is another Makefile.srcs: RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword $(MAKEFILE_LIST)))), rfnoc_block_first.v someother.v another.v) So just a list of sources When everything is in place and is working well, then I invoke the rfnoc_image_builder as such: rfnoc_image_builder -F $UHD_FPGA_DIR -I $RFNOC_OOT -y $RFNOC_OOT/icores/x310_rfnoc_custom_config.yml --vivado-path $VIVADO _PATH -t X310_XG -l DEBUG The DEBUG prints more logging information about connections made during the RFNoC core generation. If things are completely successful, then you'll get an FPGA image popped out at the end. If there are issues with sources or other problems, then you'll get some log you can try to find. Note that I believe you can issue multiple -I to pull in disparate OOT blocks and use them with the same icore yml file. Good luck. I hope this was helpful. Brian